Electronics Laboratory, Department of Electrical Engineering, University of Oulu
juha.kostamovaara
ee.oulu.fi, timo.rahkonenee.oulu.fihttp://www.infotech.oulu.fi/cas
Professor Juha Kostamovaara and Professor Timo Rahkonen,
Electronics Laboratory, Department of Electrical Engineering, University of Oulu
juha.kostamovaaraee.oulu.fi, timo.rahkonenee.oulu.fi
http://www.infotech.oulu.fi/cas
The Circuits and Systems group consists of about 40 researchers working at the Electronics Laboratory of the Department of Electrical Engineering at the University of Oulu. The group is being supervised by Professors Juha Kostamovaara, Timo Rahkonen and Jukka Lahti. Its main activity is in the field of electronic and optoelectronic circuit and system design. The primary implementations are based on various ASIC technologies. The main interest of the group is devoted to certain novel circuit topologies and functional units, although the group is also interested in applications especially in the field of telecommunications and electronic/optoelectronic measurements.
The group's work will concentrate especially on the development of high speed electronic (analogue, mixed mode and optoelectronic) circuits and systems. The main research fields are:
The most important application fields of the research results of the group are optoelectronic measuring systems such as laser radar distance measurement techniques, radio telecommunications, and the measurement and transmission of biomedical signals. In all these fields, the results have been applied in industrial R&D projects and have led to commercial use.
The group has created a well-functioning partnership with some international research units working in the same or in a complementary field. The cooperation here refers to common projects aiming at strategically common goals. The primary partners are the University of Lund in Sweden (the shared INWITE project, and the shared NorFa network on Terahertz techniques), the University of Carleton (frequency synthesis) and the A. F. Ioffe Institute in St. Petersburg (the shared INTAS project).
During 2000, the Circuits and Systems group has been funded by the Academy of Finland (1 major project, 4 GETA scholars (national graduate school on electronics and automation), 2 post doctoral scholars), the Technology Development Center of Finland (3 major projects) and industry (in connection with TEKES projects), INTAS (international cooperation project with the University of Ulm and the A.F. Ioffe Institute), European Space Agency and Infotech Oulu (direct funding and 1 Infotech Oulu graduate scholar).
In the following, the details of the work within the three research fields of the group are given: laser radar techniques and related circuits and devices, radio telecommunications and low voltage/low power circuit and system techniques.
The goal of the research has been to realize the basic laser radar functions, the receiver channel and the time interval measurement unit, as high performance integrated circuits. This should open ways to realize a laser radar as a component-like microsystem where all the basic elements (laser diode, photoreceiver(s), receiver channel(s), time interval measurement electronics) are located on a single encapsulated hybrid circuit, without sacrificing the performance of the system. This kind of technique has a lot of applications: in the measurement of level heights in silos, positioning of tools and vehicles, velocity measurements, anti-collision radars, proximity sensors, space applications etc., and the increase of the integration level makes many of these applications more appealing.
During the last year, an integrated receiver channel based on leading edge detection of a laser pulse was realized (see figure, which shows the integrated receiver together with an avalanche photo diode chip on the same hybrid). Linear processing of the pulse is not needed in this case as only the crossing of the threshold level at the leading edge is of interest. Thus the amplitude of the signal can be varied over a very wide range and the distance can be measured with a single pulse without any gain control. The method generates walk error as the amplitude of the timing pulses changes, but this can at least partly be reduced using pulse amplitude information. The receiver channel was realized in a 0.8 µm BiCMOS process. The timing error after walk and temperature compensation was measured to be below +/- 35 mm in a dynamic range of 1:4000.
The other goal of this research work has been to implement a high resolution multichannel time-to-digital converter (TDC) using standard digital CMOS technology. The measurement is based on a counter and multiphase delay line interpolation. As a result, a circuit architecture that makes it possible to realize a low power single chip time-to-digital converter with ~20 ps resolution in multiple measurement channels simultaneously has been developed (see figure, 9 channels). The automatically calibrating digital delay lines used here achieve not only high resolution but also good temperature stability which makes the circuit immune to process parameter and temperature variations. The main application for this TDC circuit is time-of-flight laser range finding measurements, especially for 3D-imaging applications where multichannel time interval measurements are required. However, many of the other published multichannel TDC circuits have been designed for nuclear science measurements for which this TDC is also suitable. In fact, the TDC to be implemented here exceeds the resolution requirements of the nuclear science measurements and also exceeds the performance of the multichannel TDC circuits published so far. Previously, we have implemented a 9-channel TDC with 625 ps resolution and a 3-channel TDC with 78 ps resolution. Now the goal is to further improve the resolution and increase the number of channels without markedly increasing the chip size or power consumption. The figure below shows the layout of a 9 channel time-to-digital converter, which is currently being processed.
During 2000, the first single laser radar ASIC comprising of 4 photodetectors, receiver channels and time-to-digital converters was tested and found to be fully operative. This chip enables four independent simultaneous distance measurements, and represents thus a milestone in the development of integrated laser radar vision chips.
One aim of the work in the field of laser radars has been to increase the speed of the laser pulse and decrease its length in order to improve the single shot accuracy, and simplify the receiver channel signal processing. Picosecond optical pulse generation by making use of the current pumped laser diodes implies typically a gain-switching operating mode. Any enhancement associated with the increase in the power density and the reduction in the pulse duration should be based on gain control or, alternatively, on the control of optical losses, which would allow significant carrier accumulation in the active region before the lasing onset occurs.
The following ways for the gain and loss control were investigated in the group within the last year. The first one, related to the gain control, is carrier accumulation in the energy space with further carrier relaxation and instant increase in the gain. The second of the suggested ways, associated with loss control, makes use of the intrinsic saturable absorber. The last one allows controlling the lasing instant precisely by change in both the absorption rate and in the refractive index, thus affecting the diffraction losses in the cavity.
Taking advantage of these mechanisms has allowed achieving 20-40 ps in duration optical pulses with power density, which exceeds by one or two orders of magnitude that achievable from various gain-switched laser diodes. In addition, new laser structures are suggested and grown aiming at the development of an optimized laser diode for high-power, short-pulsing operation together with simplified requirements for driving circuits.
Significant new results were achieved in the physical explanation of the peculiarities of avalanche transistor operation at extreme current densities. This specific mode is very important in the design of simple, advanced pumping circuits for the pumping of the gain-switched and Q-switched laser diodes. The physical reasons for low residual voltages at extreme currents were found for the first time, and a static numerical model was suggested which describes correctly the final residual voltages and shows the effect of the transistor structure parameters on the switching process. New circuit solutions, based on this specific operating mode, were lately realized and used for the Q-switched laser pumping, which has allowed an increase in the power of the picosecond optical pulse by a factor of 3.
In addition, integration of optical detectors in standard CMOS or BiCMOS processes has been studied during 2000. Here interest has been devoted to single element detectors, as well as to multi element arrays and position sensitive detectors. In the field of high speed detectors a CMOS avalanche photo diode, for example, has been designed and realized, and shown to work both in the linear mode, giving a sensitivity of 2-3 A/W, and also in Geiger mode.
A position sensitive device (PSD) is a photodiode which is capable of detecting the centroid position of a light spot falling on its active surface. PSDs are used in many commercial and industrial applications to optically measure the position of various targets. These applications include triangulation based distance sensors used in compact cameras to control lens focusing, for example. Typically, such distance sensors include a PSD chip and another chip for signal processing, both manufactured using different technologies and separately packaged. One of the goals was to implement PSDs using standard CMOS technology in order to be able to combine signal processing and sensing on a single chip. In total, twelve test devices utilizing seven different constructions of CMOS compatible PSDs were implemented using standard 1.2 µm, 0.8 µm and 0.6 µm CMOS technologies. Half of the test devices utilized the current division principle similar to that used in discrete PSDs, but in addition to the conventional continuous (lateral effect photodiode) structure, PSDs based on dense photodetector arrays were implemented. The other half of PSDs composed of active pixel photodetector arrays (see in the figure an array with 32*32 photodetectors) with one bit AD converter embedded in each pixel. The results show that it is possible to implement high performance PSDs using CMOS technology and that their performance can be even better than those of conventional ones although conventional PSDs are manufactured using dedicated processes. An order of magnitude improvement in incremental sensitivity and also considerable improvement in linearity were achieved with the array type PSDs, for example. These results are described in more details in the doctoral thesis of Anssi Mäkynen, which was accepted in 2000.
The integrated RF synthesizer designed during the previous year was tested in 2000. Special attention was paid to the verification of the new structures for speeding up the frequency step response of the loop (see figure below). According to the measurements, it is possible to make the transient response of an integer-N based PLL faster using simple current waveforms which control the charge stored in the loop filter capacitors during frequency transition. The functionality of the speed-up ideas was proven using measurements which match the corresponding theoretical and simulated results reasonably well. The recommended waveform consists of just two current pulses and is thus attractive for further integration.
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During the year 2000, a second test chip on 
-modulators, based on SSCT switched capacitor
integrator topology was designed. The simulated performance of the five modulators realized was
10bits@271kHz with PSRR of ~44dB.
The design method of the first test chip was rather aggressive; the main emphasis was on low power consumption and a small silicon area. In selected topology, there is an inherent contradiction in design requirements between achievable SNR/PSRR and the tolerated current consumption. The increase in PSRR increases the silicon area and power consumption, and vice versa. The measurements revealed that the circuits had unexpectedly large sensitivity to the noise in supply lines and component mismatch. These resulted in an 8dB loss in SNR/PSRR when compared to the simulation results, and relatively large offset voltage.
The improvement in performance can be obtained by balancing the structure, using error sampling/feedback or by using excessive filtering. Since the balancing more than doubles the area and the current consumption, and since the balancing is not required to improve distortion, it was seen that the preferable way to improve the performance is to use a single-ended structure with some modifications. In the resulting new design, simulated PSRR was improved by 10dB at the cost of a 30-50% increase in current consumption. The aliased HF-noise is attenuated by increasing the size of the filtering capacitors. Since the filtered signals are DC-signals, the filtering effects only the silicon area of the realization. The total area of the modulator increased 150%.
Two new complex signal processing structures, a quadrature subsampler based on current signal sampling and a complex bandpass filter based on switched-capacitor (SC) techniques, have been suggested and analyzed, especially from the noise performance point of view. The analysis shows that by using the current-mode sampler presented, with an associated FIR-type filtering effect for I/Q downconversion in a radio receiver, a low noise figure can be obtained. In addition, the performance of the integrated test circuit realized in a 0.8 µm BiCMOS process and the correctness of the noise analysis presented is determined by measurements. The measurements show a 43 dB image rejection and a 9.8 dB spot noise figure at the center frequency of the signal band and a -32 dBm third-order input-referred intercept point (IIP3) for the circuit.
Linearization of RF power amplifiers (PAs) has grown to be an extremely important topic for future bandwidth-efficient wireless solutions, as good linearity required by efficient modulation schemes or multicarrier transmitters usually means intolerably low efficiency. Predistortion type linearisers have been studied in the group for some years, and a new, analog polynomial baseband/IF predistorter IC has been designed. It includes some built-in filtering that can be used to extend the usable bandwidth by compensating bandwidth-dependent distortion or so-called memory effects.
It has been discovered that the memory effects in the PAs, or anywhere between the lineariser and the PA, seriously affect the performance of the linearisers, both analog and digital predistortion, and feedforward systems). For this reason, a lot of effort has been made to identify the causes of memory effects in power amplifiers. Volterra analysis has been used to separate the different distortion mechanisms, their amplitudes and phases, and especially to find how the distortion behaves with varying signal bandwidth and amplitude, or how it depends on terminal impedances around DC or the harmonic frequency zones. To streamline Volterra analysis, a characterisation technique has been developed where small-signal s-parameters measured on a dense grid of bias points are used to extract a polynomial ac-model of the transistor. Simulated results based on the extracted values match very well with data measured and can be used to find proper harmonic matching impedances or dominant causes of memory effects. To make Volterra analysis of large circuits easier, a generic Volterra simulator with a Spice netlist to an MNA matrix parser has been written in a Matlab environment. It has been used to see the dominant cause of distortion in active filters and balanced amplifiers, for example.
Memory effects have been characterized by measurements, too. A novel test setup for measuring the optimum predistortion signal has been developed, and has clearly shown how the phase of IM3 distortion components can vary with signal bandwidth due to frequency dependent biasing impedances or self-heating at the modulation rate. The thermally induced distortion has been successfully reduced by a setup called the envelope injection technique where the input RF signal is rectified, shaped with a simple low-pass filter and summed to the input bias voltage, from which it up-converts to IM3 and cancels the thermally induced distortion in the 100 Hz-1MHz region around the carrier. A simple polynomial RF predistorter has been used to cancel the non-frequency dependent portion of IM3 distortion. Altogether, 5 papers about memory effects have been presented or accepted, and three more were submitted during year 2000.
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| Measurement setup for measuring the phase of IM3 distortion components in an RF amplifier. A separate tone at 2w1-w2 is used to cancel distortion, and cancellation is used to measure the phase of the IM3 component. |
Various baseband signal processing blocks have been tested. A DDS clock generator where the sinewave look-up-table and D/A converter have been replaced by a time domain interpolator has been found useful in baseband timing operations, for example, for correcting Doppler shift, and a new, improved version based on a 3-stage, 130-ps/step digital delay generator has been designed and tested. It is capable of producing 015 MHz (in 2 Hz steps) square wave output with -50 dBc spurious level, but does not need a D/A or any reconstruction filtering.
Analogue circuits
Low voltage (1-1.5 V) basic analog signal processing elements, such as operational amplifiers, bandgap reference circuits and oscillators used in the processing of biomedical signals (100 Hz ...1 kHz) have been studied and implemented. A test chip containing an RC-oscillator and a bandgap reference has been designed and sent to be processed in 0.35 µm CMOS technology. Both circuits have been designed to operate with 1 V supply voltage. Furthermore, a low power gm-C bandpass filter with 3 V supply was designed and implemented. This design has been sent to be processed in 0.6 µm CMOS technology.
The design goals for the RC-oscillator were: an operating frequency of 5 MHz with ± 5% accuracy, jitter < 0.2 ns, pulse ratio of 47-53% and current consumption < 40 µA in a temperature range of 0-50 oC. The RC-oscillator consists of a 5-stage current starved ring oscillator topology and a control circuit which are in a feedback loop with an off-chip resistor and capacitor. The reason for using an outer resistor and capacitor is accuracy. With outer components having an absolute accuracy of ± 1% the design goals are met. The control circuit compares the output frequency of the ring oscillator with the outer RC time constant. As long as the frequency differs from the desired one the control circuit adjusts the frequency of the oscillator. The control circuit also makes this design insensitive to supply voltage, temperature and process variations. Currently also a 32.768 kHz crystal oscillator topology is being designed.
The designed gm-C bandpass filter is a differential 6th order elliptic biquad filter consisting of three 2nd order blocks (a bandpass filter, a lowpass notch filter and a highpass notch filter) in series. The filter employs a tuning circuit, which adjusts the internal gm/C-ratio i.e. the center frequency of the filter with an external 32.768 kHz reference clock. The circuit is optimized with respect to its power consumption, the figures being 3 V and 30 µA.
Low-power architectures and building blocks for digital telecommunication ASICs
The aim of this research topic has been to develop digital communication methods and circuit realizations for a wireless data transmission application where multiple independent transmitters send data to a receiver asynchronously in the same frequency band. In addition to these transmitters, other transmitters communicating with a different receiver maybe interfere with the data transfers.
The radio modulation technique in the system is a variation of amplitude shift keying (ASK). For this reason, conventional CDMA techniques can not be directly used to solve the problem, since only one code symbol ("1") is available instead of two ("1" and "-1"). Earlier, various coding schemes have been studied, and computer programs for code generation, and a test system for code performance evaluation in practice have been developed. In 2000, the performace of different coding methods has been studied, using the test system.
Specific research topics in 2000 have been:
The main results of the project are:
During, 2000 the group organized a graduate course under the title "Analysis of distortion in analog integrated circuits" gathering roughly 20 listeners in January and it was held again in a slightly revised form in the University of Lund, Sweden, in April 2000.
Results of the research have been applied by Nokia Mobile Phones, Nokia Networks, Noptel, Polar
Electro and Fincitec, for example, who also have been funding the work.
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professors & doctors |
8 |
|
graduate students |
14 |
|
others |
20 |
|
total |
42 |
|
person years |
32 |
|
Source |
FIM |
|
Academy of Finland |
1 688 000 |
|
Ministry of Education |
424 000 |
|
Tekes |
2 745 000 |
|
other domestic public |
80 000 |
|
domestic private |
1 242 000 |
|
EU + other international |
381 000 |
|
total |
6 560 000 |
Räisänen-Ruotsalainen E, Rahkonen T & Kostamovaara J (2000) An integrated time-to-digital converter with 30 ps single-shot precision. IEEE Journal of Solid-State Circuits 35(10): 1507-1510.
Mäntyniemi A, Rahkonen T & Kostamovaara J (2000) Integrated digital CMOS time-to-digital converter with sub-gate-delay resolution. International Journal on Analogue Integrated Circuits and Signal Processing 22(1): 61-70, Kluwer Academic Publishers.
Palojärvi P, Ruotsalainen T & Kostamovaara J (2001) Pn photodiodes for pulsed laser rangefinding applications realized in standard CMOS/BiCMOS processes. International Journal on Analog Integrated Circuits and Signal Processing 27(2): 237-246, Kluwer Academic Publishers.
Kostamovaara J, Mäntyniemi A, Palojärvi P, Peltola T, Ruotsalainen T & Räisänen-Ruotsalainen E (2001) Integrated chip set for a pulsed time-of-flight laser radar. Proceedings of the SPIE Optoelectronics 2001 Conference in Photonics West, January 22-28 2001, San Jose, USA, 15 p.
Vainshtein S & Kostamovaara J (2000) Transient spectrum relaxation in Q-switched laser diode with intrinsic absorber. Proceedings of the SPIE Optoelectronics 2000 Conference (Integrated Optoelectronic Devices) in Photonics West 3940: 192-199, January 22-28, San Jose, USA.
Peltola T, Ruotsalainen T, Palojärvi P & Kostamovaara J (2000) A receiver channel with a leading edge timing discriminator for a pulsed time-of-flight laser radar. Proceedings of the 26th European Solid-State Circuits Conference, ESSCIRC´2000, Stockholm, Sweden, September 19-21, 4 p.
Karvonen S, Riley T & Kostamovaara J (2000) A Hilbert sampler/filter and complex bandpass SC filter for I/Q demodulation. Proceedings of the 26th European Solid-State Circuits Conference, ESSCIRC´2000, Stockholm, Sweden, September 19-21, 4 p.
Rahkonen T, Kankaala T, Neitola M & Heiskanen A (2000) Using analog predistortion for linearizing class A - C power amplifiers. International Journal on Analog Integrated Circuits and Signal Processing 22(1): 31-40, Kluwer Academic Publishers.
Vuolevi J, Rahkonen T & Manninen J (2000) Measurement technique for improving linearity by optimizing the source impedance of RF power amplifiers. In Proc. 2000 IEEE Radio and Wireless Conference (RAWCON00), Denver, Colorado, USA, September 10-13, 227-230.
Vuolevi J, Rahkonen T & Manninen J (2000) Measurement technique for characterizing the memory effects in RF power amplifiers. In Proc. 2000 IEEE Radio and Wireless Conference (RAWCON00), Denver, Colorado, USA, September 10-13, 195-198.
