Circuits and Systems (CAS-Oulu)

Professor Juha Kostamovaara and Professor Timo Rahkonen,
Electronics Laboratory, Department of Electrical and Information Engineering, University of Oulu
juha.kostamovaaraee.oulu.fi, timo.rahkonenee.oulu.fi
http://www.infotech.oulu.fi/cas

Background and Mission

The Circuits and Systems group consists of about 40 researchers working at the Electronics Laboratory of the Department of Electrical Engineering at the University of Oulu. Its main activity is in the field of electronic and optoelectronic circuit and system design. The primary implementations are based on various ASIC technologies. The main interest of the group is devoted to certain novel circuit topologies and functional units, although the group is also interested in applications particularly in the field of telecommunications and electronic/optoelectronic measurements.

The group's work concentrates mainly on the development of high speed electronic (analogue, mixed mode and optoelectronic) circuits and systems. The research fields are:

• time-to-digital and digital-to-time converters, i.e. time interval measurement devices and controllable delay generators
• timing discriminators, especially optical receivers and detection of the timing of the received optical pulse including the realization of the optical detector (single element, mosaic, position sensitive) in standard CMOS/BiCMOS technologies
• high power laser diode transmitters including high-speed, high-current laser drivers
• development of laser radar techniques, particularly for industrial measurements, using the results of the above research activities
• radio telecommunications, including linearization of power amplifiers, frequency synthesis and AD/DA conversion and baseband blocks
• low power/low voltage signal processing blocks and their integrated circuit realizations, e.g. for biomedical applications

The group has created a well-functioning partnership with some international research units working in the same or in a complementary field. The primary partners are the University of Lund in Sweden (a joint EXSITE project, and the shared NorFa network on Terahertz techniques), the Royal Institute of Technology in Sweden (a joint EXSITE project), Carleton University in Canada (frequency synthesis), University of Kassel in Germany (a shared INTAS project) and the A. F. Ioffe Institute in St. Petersburg (a shared INTAS project).

Scientific Progress

During 2002, the Circuits and Systems group has been funded by the Academy of Finland (2 major projects), the National Technology Agency - TEKES (3 major projects), industry (in connection with TEKES projects), INTAS, NASA (Jet Propulsion lab.), Infotech Oulu (3 graduate scholars, 1 post doctoral scholar and direct funding) and the Graduate School in Electronics, Telecommunications and Automation - GETA (2 scholars).

In the following, the details of the work within the four research fields of the group are given for a selection of important research fields.

Time-to-digital conversion (TDC) techniques

The goal of this work is to develop circuit architectures suitable for multichannel time interval measurement using low-cost CMOS technology. The use of CMOS also leads to small area, low power and good stability when delay locked delay lines are used, since all the delay elements used for signal timing are locked in the same stable external frequency reference, thus providing autocalibration. The operation of the TDC is based on synchronous counting and asynchronous interpolation. The counter provides a large dynamic range. High resolution is achieved with multi-stage interpolation based on nested delay-locked loops (DLL), which allows for a high interpolation ratio, i.e. the counter clock cycle is divided into 512 bins with a reduced number of delay cells and registers.

An integrated 9-channel time interval digitizer with a 496 µs dynamic range and ~30 LSB ps resolution with a 66 MHz reference clock was implemented to demonstrate the feasibility of the architecture. The block diagram of the TDC is presented in the figure below.

As the time resolving resolution of time digitizers improves, the attainable single-shot precision of a time digitizer based on a counter and interpolators becomes limited by the integral nonlinearity (INL) of the interpolators. The INLs of the interpolators can be stored in a look-up table (LUT) and used as a correcting vector in the measurement result calculation to improve the single-shot precision. To make the nonlinearity correction efficient and practical, it would be preferable if a single correction table could be used for a circuit in any ambient temperature without having to measure the operating conditions or readjusting the correction parameters. This can be achieved if the interpolator gain, offset and nonlinearity are constant in a wide temperature range; this can be realized by using delay-locked delay lines, as is done in this work. This correction table can be collected during a one-time calibration cycle in which a large number of measurements with timing signals asynchronous with respect to the reference clock are made. The timing signal hits to each LSB are collected, the INL of the interpolators is calculated and the LUT is stored.

The equation below shows the principle of the nonlinearity correction algorithm to produce the corrected time interval measurement result T[i] with improved single-shot precision. T[i] = CTR[i]*N + (ST[i] - ST_INL[ST[i]]) - (SP[i] - SP_INL[SP[i]]), where CTR[i] is the current counter value, N is the number of LSBs in the interpolators, ST[i] and SP[i] are the current start and stop interpolator values and ST_INL[ST[i]] and SP_INL[SP[i]] are the start and stop interpolator INL values picked from the LUT addresses pointed to by the current interpolator values.

The method was tested with a CMOS time digitizer IC with a 496 µs range, 29 ps LSB resolution and 28 ps rms single-shot precision without the INL correction. The worst-case single-shot precision of 35 ps caused by the INL of the interpolators was reduced to  20 ps in the whole temperature range of -40 °C to +60 °C, as seen in the figure below, by using a single calibration LUT which contains the INLs of the interpolators measured in the room temperature.

Development of customized high-speed optical detectors in CMOS and BiCMOS technologies, and test methods for photo-detector characterization

Methods for improving the speed of CMOS-compatible pn-photodiodes have been studied. These include lowering junction capacitance by using special layout techniques, implementing traveling-wave photodiode arrays (TWDA) and studying pn-photodiode performance in the so-called Geiger-mode. In the first case, the anode or cathode of the photodiode is made mesh shaped. The mesh pattern makes the average doping concentration lower and by decreasing the feature size of the mesh beyond the design rules it is expected that, due to lateral diffusion, the doping will also become fairly uniform. The idea behind TWDAs is the same as that commonly used in microwave distributed amplifiers. The TWDA embeds several small optical detectors within a microwave transmission line structure that coherently combines their photocurrents while retaining their high bandwidth. This artificial transmission line is tuned to have a 50 Ω impedance by balancing the detector capacitances with appropriate series inductances. The optical signal is distributed to the detectors in the proper RF phase using tailored length optical fibers such that the electrical signal delay between detectors is matched by the optical delay between the fibers. In Geiger-mode, the reverse bias of a photodiode is raised a few volts above its breakdown voltage. Due to the large electric field, charge carriers generated in the depletion region are capable of generating a large number of new carriers by ionizing silicon atoms during collisions. This results in a large breakdown current which can be easily detected. Besides high speed (a few tens of ps rise time), the Geiger-mode provides basically single photon sensitivity with very high gain. The purpose is to characterize the Geiger-mode operation of a few CMOS/BiCMOS-compatible avalanche photodiode structures. The critical performance parameters include quantum efficiency, dark count rate, response speed and jitter. All photodiode structures have been implemented using standard BiCMOS technology and their characterization is in progress.

Experimental avalanche photodiode structures. A, D and E are CMOS-compatible. B and C can be implemented in standard BiCMOS.

A measurement system for electro-optical characterisation of photo-detectors and photo-detector arrays has also been implemented. The system is intended for laboratory use where typically a batch of a few devices are characterised at a time. The instrument is used for measuring the spectral, spatial and temporal response of a single photo-detector or a photo-detector array as a function of wavelength and temperature. In the case of photo-detector arrays, also modulation transfer function (MTF) can be measured at desired wavelength. Most measurements can be performed fully automatically.

In addition, the performance of a random target method for fast MTF measurement of a lens has been evaluated. The method is well known, but its potential for fast lens testing has not been assessed in the open literature before. The set-up of the random target method needs only a few components, and it provides high speed since a minimum amount of mechanical movements are needed during measurement execution. The setup includes only a random target, an illuminator, a fixture for the lens to be tested and a CCD camera with motor actuated focus adjustment. The target consists of a random black and white pattern of a flat spectrum. The MTF of the lens is acquired by imaging the random target on the CCD using the lens under test, and then analyzing the spatial frequency content of the image using a computer. It was found that a reasonable compromise between speed and precision is achieved using 128*128 samples per measured field point. This provides precision greater than 2% and a total execution time of a few seconds per lens, including best focus evaluation and the measurement of tangential and sagittal MTF curves of 5 field points. Using commercially available components, a measurement range up to 100 cycles/mm seems achievable, which is enough for low-cost lenses.

Picosecond laser pulse generation and high speed switches

A mechanism of field-assisted gain control was suggested and implemented in a new laser diode design for high-power picosecond pulse generation. This mechanism consists of effective gain control in a specific double-heterostructure caused by the transverse electric field. The proposed type of the laser diode can be realized on the basis of various semiconductor materials, thus providing the means for generating ps pulses of high power density with a controllable wavelength. One important advantage of this light source lies in the fairly moderate requirements on the speed of the current driver so that the direct current pumping can be realized using simple drivers based on a commercial avalanche transistor. This has become possible due to the specific internal optical pumping realized in the diode structure. The generation of 50 W / 20 ps optical pulses has been experimentally demonstrated for the first laser prototype based on an AlGaAs/GaAs system. The simulations of the laser diode were performed using an ATLAS device simulator (Silvaco Inc.). The simulations have demonstrated reasonably close agreement with the experimental data and provided conclusive confirmation for the suggested mechanism of field-assisted gain control.

Principle of operation of a new laser diode and time-resolved spectra of the laser response.

A related topic is an investigation of the switching-on transient in a high-current Si avalanche transistor, used for the pumping of a picosecond laser diode. The theoretical and experimental study has shown that high-current nanosecond switching occurs in an n⁺-p-n₀-n⁺ Si transistor structure and cannot be realized in the inverted p⁺-n-p₀-p⁺ transistor due to the differences in the electron and hole mobilities. This important general conclusion has changed common opinion existing for many years that n-p-n Si transistors are more prone to non-thermal secondary breakdown than p-n-p transistors due to the difference in ionization coefficients between electrons and holes. A 1D dynamic model of the avalanche transistor has shown that fast (nanosecond) high-current switching of an n⁺-p-n₀-n⁺ structure with low residual voltage occurs due to the formation and fast spread of a quasi-neutral region in the collector domain. Further consideration of the switching transient in 2D dynamic simulations using the ATLAS device simulator has provided excellent agreement with the experimental data and shown a few important features of the process: e.g. a powerful current localization was found in the structure during the switching transient, which determines very high carrier concentration in the switching channel and strong spatial localization of the region of intensive heat generation. The data obtained from 2D modeling allows reliable analyses to be performed of the temperature dynamics in the structure and to draw conclusions concerning such an important parameter as the maximum achievable repetition rate of the current pulses. Furthermore, the achieved understanding of how the material parameters affect the switching transient opens up new horizons for the designing of high-speed avalanche switches based on materials other than Si. It was shown, for example, that the carrier density in the switching channel can exceed the transparency concentration in the direct-band semiconductor (e.g. GaAs), so that the stimulated emission and light re-absorption could play an essential role in the speeding up of the switching process.

Electric field (a) and carrier density (b) profiled in the switching channel during the high-current switching transient in a Si avalanche transistor.

Laser rangefinding techniques and related circuits

A laser rangefinding module based on a pulsed time-of-flight (TOF) distance measurement technique was constructed and tested. The aim - mm-level measurement accuracy with low power consumption, cost and size - was achieved using full-custom application-specific integrated circuits in significant parts of the device, the receiver channel and the time-to-digital converter (TDC). The ASICs have been developed in earlier projects and now their performance has been verified in a real rangefinding device. Especially the size and power consumption represented significant reductions relative to earlier discrete realisations. The dynamic range of the optical input signal was increased by means of a current-mode gain control at the input of the amplifier channel. The accuracy of the device with the optomechanical head used in the measurements is at the mm-level in the case of a non-cooperative target at a measurement range from 4 to 34 m, and at a temperature between -10°C and +50°C. The power consumption in continuous measurements at a pulsing frequency of 10 kHz is 3.9 W.

During the year, a CMOS circuit for a pulsed time-of-flight laser rangefinder was processed and tested. In the circuit, a transimpedance amplifier channel, a leading edge timing discriminator and a time to digital converter (TDC) were integrated into the same chip aiming at the further increase of the system integration level of a laser radar. The TDC is based on a new idea of timebase. A free running, high-frequency oscillator is used as a clock for the TDC and is being calibarated with an accurate, low-frequency oscillator. The circuit was implemented using 0.35 µm CMOS process. The error in distance measurement applications is on the cm-level, and the precision of a single measurement result is about 1 cm.

Frequency synthesis

Frequency synthesizers are used extensively in modern radio telecommunications equipment in the channel selection structures, for example. One of the goals of the work done in the electronics laboratory has been to construct a test and evaluation system for the most common single loop PLL-type synthesizer architectures, namely the integer-N, fractional-N and -modulated PLL synthesizers.

The test system is built around a general purpose fast-switching full-custom PLL IC designed in a 0.8 µm BiCMOS process (5V/80mA/2.8x3.3mm²). The circuit provides the phase-frequency detector (PFD) and charge pump structures of a typical PLL, and some supplementary electronics, which realize the new two-pulses speed-up method. The actual synthesizer evaluation system was built around the PLL IC using a commercially available low phase noise divider and voltage controlled oscillator (VCO).

An FPGA based modulator prototyping system needed for modulated PLL synthesizers forms the second major component of the synthesizer evaluation system. This prototyping system enables fast prototyping of different modulators using VHDL synthesis and the implemented design verification framework. An example 3rd order modulator with suitable noise shaping properties was implemented and used in measurements.

The measured phase noise of an integer-N synthesizer with f_ref = 13 MHz and N=126, for example, was 93.4 dBc/Hz @ 1.5 kHz and 102.3 dBc/Hz @ 10 kHz. These values give as a figure of merit, a 1 Hz normalized PD noise floors of -207 dBc/Hz and -215 dBc/Hz, respectively. The level of the 1st (=highest) spurious with no extra attenuation provided by notches or additional RC-LP-filtering, was -67 dBc. Measurements show that the speed-up scheme works also in the context of modulated synthesizers, even though work towards an optimal synthesizer still continues.

Synthesizer research is currently proceeding towards new synthesizer architectures commonly referred to as 2^nd generation synthesizers. In these architectures, the loop is arranged in such a way as to avoid some of the most stringent problems of the traditional loops, such as the multiplication of phase noise inside the loop bandwidth, for example. Additionally, most of the signal processing in done in DSP, which offers increased flexibility, accuracy and the possibility of advanced loop control. The goal is to develop and realize new loop components and architectures, the performance of which can readily be compared to the performance of traditional synthesizers with the help of the above mentioned evaluation system.

Linearisation of RF Power amplifiers

One of the main problems in modern RF transmitters is to combine high linearity with reasonable efficiency. In general, this can not be achieved without the use of some external linearisation technique like Cartesian feedback, for example. Analog or digital predistortion are very power effective and tempting linearisation techniques, but, as open-loop systems, they necessarily rely on some assumptions about the behaviour and predictability of the power amplifier. The immediate goal of this research is to be able to understand and minimise the bandwidth dependency of the distortion in power amplifiers, so that the predistortion system is easier to build and train. A broader aim is to be able to understand nonlinear phenomena in general, and find ways of utilising available cancellation mechanisms to reduce distortion.

The power amplifier related work has been going on for several years, and the results so far were documented during 2002 in a book entitled "Distortion in RF Power Amplifiers", that appeared from Artech House in February 2003.

Detailed distortion analysis

To study the fine structure of distortion components, a new electro-thermal circuit simulator has been developed. It can display the distortion products as sums of contributions, exactly as designers see them in noise simulations - for example, we can immediately see how much of the total third harmonic is caused by the second-degree nonlinearity of the input impedance that generates a second harmonic into the input node and mixes it further to the third harmonic. Unlike noise, distortion consists entirely of correlating signal components, in which case both the magnitude and the phase of the distortion components are important. This information is most naturally preserved by plotting the contributions as vectors, and from the vector plots it is easy to recognise which contributions cancel, and which ones amplify each other.

The simulator is based on numerical Volterra analysis of discrete tone test signals. The calculation technique is based on numerical convolution of input spectrums, and it is not inherently limited to one- or two-tone cases. Instead, we can, for example, study what effects a harmonic injection has on the total distortion. The simulator has a fifth-order electro-thermal kernel, and it is currently written in a Matlab environment. It will be used to study the possible distortion cancellation schemes of some typical architectures.

Fine structure of IM3 distortion tone in an LDMOS power amplifier. Terms K300 and K120 (vin3 and vin*vout2) partially cancel each other.

Device modelling

The Volterra analysis used in the distortion calculations is based on the use of polynomial AC device models, as this allows tractable calculation of spectral regrowth. Polynomial models are not commonly available, however, so model characterisation techniques had to be developed. The models are formed simply as a polynomial fitting to I-V, Q-V, C-V, or G-V data measured over a given range of controlling voltages. The fitting itself is a standard LMSE fitting process, where numerical accuracy can be improved by the selection of the data range, normalisation techniques, and QR factorisation, for example. To obtain the data, an automated measurement setup has been built that performs pulsed (isothermal) s parameter and current measurements over a chosen range of bias points.

Digital error correction of analog-to-digital converters

The matching accuracy of passive components tends to limit the resolution of multi-bit A/D converters to 9-11 bits. Moreover, good matching requires large devices, and this increases the capacitive load and hence the power dissipation of the amplifiers. This research seeks ways to reduce the power consumption of A/D converters by using digital error correction techniques. This is done by analysing the effects of various mismatch and settling errors, and by developing digital compensation techniques for reducing them.

Settling of SC amplifiers

The settling of switched capacitor amplifiers or integrators is a complex nonlinear phenomenon, and settling errors are usually minimised by quite conservative design, where large bias currents are needed especially to achieve a high slew-rate. The settling starts from an initial point which depending on the amplifier topology, may be a function of the input voltage only, or also a function of the previous output state.

To make behavioural simulations faster, a new measurement-based modelling technique was developed: the settling error of the amplifier is simulated (either using a state-space model of required complexity, or an existing transistor level schematic) as a function of the initial point. This error is fitted to a 2-dimensional polynomial function that can be used as a behavioural model of the amplifier.

Digital error correction of multi-bit sigma-delta A/D converters

One way of increasing the resolution and reduce the oversampling ratio of oversampling sigma-delta A/D converters is to employ multi-bit feedback. Unfortunately, this is sensitive to linearity errors in the feedback D/A converter, and even a modest amount of INL mixes the quantisation noise back down and reduces the signal-to-noise ratio. Here, a fully digital error correction technique has been studied, where the linearity errors of the D/A converter are estimated and cancelled in the digital domain.

The error correction technique itself is functional and quite easy to implement: the actual level of the feedback signals is measured or estimated, and the error compared to the ideal levels is subtracted from a digital output signal. However, the estimation of the errors is trickier. Three techniques have been studied: an off-line calibration measurement of the feedback levels; an on- the-fly measurement of the element errors that requires some redundant DAC elements and a shadow A/D converter; and last, a blind adaptation technique that correlates the noise floor with the levels of the feedback DAC and this way finds the correct weights for each feedback level.

Training circuit for error correction of pipeline AD converters

Another interesting type of A/D converter is a pipeline A/D that can be used to sample rates of tens or hundreds of MS/s. Pipeline A/D converters typically always employ some redundancy and digital error correction that can correct some types of error, and techniques capable of correcting all static errors are commonly known - in the most typical form, the actual weights of a few msb stages are measured, and these weights (instead of plain powers of two) are used to build the binary output.

A real-time training system for digital error correction has been built. It consists of a digital two-tone sine generator, commercial D/A converter, pipeline A/D converter to be calibrated, and a real-time INL error calculation block that makes an ideal digital fit to the measured signal and outputs per-sample INL information as a difference of the fitted reference signal and the measured signal. The real-time INL information is used to adapt the error correction block, and the adapted correction coefficients are used to correct the output. Both the coefficients and either the uncorrected or corrected data can be exported from the system. So far, the system has been tested with two integrated pipeline A/D converters, and both of them seemed to have quite strong dynamic errors, indicating that the commonly used static error correction is not sufficient.

The block diagram of the ADC error correction training circuit.

Analog reconstruction and channel selection filters

The output signal of a D/A converter contains spectral images around all clock multiples. To attenuate the first image signal, a new filtering technique has been experimented. It is based on placing the first notch of the sinx/x type output frequency response over the first image band. This is achieved by extending the hold time of the D/A converter beyond a one clock cycle: by employing two time-interleaved D/A converters, the outputs of which are partially overlapping and summed together. A test system with programmable hold time has been built, and it proved the functionality of the concept: the first image was attenuated by an additional 15 dB compared to the normal zero-order hold response.

Time-interleaved systems are sensitive to gain and timing mismatches between the parallel branches, and this applies to this design too: a mismatch in the one-time of the A/D converters causes rather high -45 dBc half-rate spurious images.

Another filtering application was an analog baseband FIR type receiver filter for WCDMA, with a sampling rate of 16 MHz and a bandwidth of 2 MHz. It is implemented as a bank of 4 samplers, where the weights of the samples are fixed (1-2-2-1) but the sampling instants can be programmed to control the frequency response of the filter. As the length of the impulse response can be several clock cycles, altogether eight time-interleaved sampler banks are needed. This filter has been implemented as an integrated circuit, and it operates as expected.

Low voltage/low power analogue circuit techniques

In this field, low voltage (1-1.5V), low power (mW-range) analog signal processing elements have been studied and implemented. These circuit blocks are intended to be used in portable biomedical and audio applications like heart rate detectors, pace makers, hearing aids etc. In portable applications minimization of the power consumption is essential. Most often the supply voltage is provided by a dry-cell battery or a rechargeable battery, which means that the supply voltage is relatively small. In future, the maximum allowable supply voltage will also be process technology-limited, since the breakdown voltages of the MOS-transistors will also scale down with the reduced line widths. Therefore the development of single battery cell (1-1.5V) analog circuit blocks is seen to be important. As a result, circuits like operational amplifiers, voltage references and crystal/RC-oscillators have already been implemented and published.

In traditional operational amplifier topologies, the low supply voltage causes several problems, like reduced signal swing at the input/output, decreased SNR and reduced gain. The signal swing at the input is limited because of the threshold voltages of the input transistors. This problem has been overcome by modifying the input stage in such a way, that it will reduce the effective threshold voltages of the input transistors. This has been done in two different ways; by using floating-gate (FG-MOS) input transistors or by using bulk-driven (BD-MOS) input transistors. In the first option, the threshold voltage of the MOS-transistor is modified by a dc-voltage bias, which is imported capacitively (through a capacitor) to the floating gate of the MOS-transistor. Then the signal is applied to the floating gate by another capacitor. In the second option, the gates of the input transistors are connected to a dc-voltage bias and the signal is applied to the local substrates (bulk-terminals) of the input transistors. In both ways, almost rail-to-rail input signal operating range has been achieved. Another problem of designing low voltage operational amplifiers is that cascode-transistor structures cannot be used, because of insufficient voltage headroom. If simpler single-transistor structures are used, in many cases the gain of the amplifier will be too small. In order to increase the gain, multiple amplifier stages can be cascaded, but then the compensation of the amplifier becomes more complex. Some new compensation techniques have therefore been developed and implemented, and the measurements have shown good results. At the moment, the work is focused on implementing a larger integrated system, a biosignal detector, which comprises the developed low voltage circuit blocks. The system includes the necessary amplifier structures, an SC-filter, a crystal oscillator and a bias-circuit. This work will be ready in 2003 and the results of the work will be published later.

Another focus of interest has been in developing a low power 3-V 6th-order continuous-time transconductor-capacitor (gm-C) filter for a portable biomedical application. The aim of this work was to study the possible advantages of a gm-C filter with respect to a previous SC-implementation in an application with low power and area requirements, but relatively low performance demands. The results of the first chips were promising and some improvements have been applied to the new design.

Post-graduate courses

To make the research more widely known to the designers in the industry, a 25-hour graduate course "Error correction in Analog-to-Digital and Digital-to-Analog Converters" was arranged by the group in January 2002. This lecture course was given by Prof. Rahkonen.

A post graduate course on "Radio Frequency IC Design" given by Prof. John Long from the Delft University of Technology was arranged by the group in November 2002.

Exploitation of Results

Results of the research have been applied by Nokia Mobile Phones, Nokia Networks, Noptel, Polar Electro, National Semiconductors Finland, and Elektrobit, who have also been funding the work.

Personnel

External Funding

Häkkinen J (2003) Integrated RF building blocks for base station applications. Acta Universitatis Ouluensis C177.

Selected Publications

Mäntyniemi A, Rahkonen T & Kostamovaara J (2002) An integrated 9-channel time digitizer with 30 ps resolution. IEEE International Solid State Circuits Conference, Digest of Technical Papers, San Francisco, CA, USA, 1: 266-267, 465.

Mäntyniemi A, Rahkonen T & Kostamovaara J (2002) A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision. IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, USA, 1: 513-516.

Vainshtein S, Sverdlov M, Shestak L, Tretyakov V & Kostamovaara J (2002) First observation of the short-pulsing Q-switching mode in a double-heterostructure laser diode without ion implantation, Proc. of SPIE 4643, 215-222.

Vainshtein S, Kostamovaara J, Sverdlov M, Shestak L, Tretyakov V (2002) Laser diode structure for the generation of high-power picosecond optical pulses, Appl. Phys. Lett. 80(24): 4483-4485.

Vainshtein S, Yuferev V & Kostamovaara J (2002) Properties of the transient of avalanche transistor switching at extreme current densities. IEEE Trans. on Electron Devices 49(1): 142-149.

Mäkynen A, Backman S & Kostamovaara, J (2002) Measurement system for photodetector characterization. Proceedings of SPIE, Opto-Ireland 2002: Optics and Photonics Technologies and Applications 4876: 1084-1090.

Palojärvi P, Määttä K & Kostamovaara J (2002) Pulsed time-of-flight laser radar module with mm-level accuracy using full custom receiver and TDC ASICs. IEEE Transactions on Instrumentation & Measurement 51(5): 1102-1108.

Riley T & Kostamovaara J (2002) A hybrid fractional-N frequency synthesizer. Accepted to be published in IEEE Transactions on Circuits and Systems II.

Häkkinen J & Kostamovaara J (2002) Speeding up an integer-N PLL by controlling the loop filter charge. Accepted to be published in IEEE Transactions on Circuits and Systems II.

Karvonen S, Riley & Kostamovaara J (2002) Charge sampling mixer with delta-sigma quantized impulse response. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2002), 26-29 May, Scottsdale Princess Resort, Scottsdale, Arizona, USA, 4p.

Tuikkanen T, Kivi A & Rahkonen T (2002) A double sampling 8-bit, 50 MS/s, 32 mW pipeline converter with +6dB overdrive headroom. Kluwer Academics journal on Analog Integrated Circuits and Signal Processing 30(1):7-14.

Vuolevi J & Rahkonen T (2002) Extraction of nonlinear AC FET model using small-signal S- Parameters. IEEE j. IEEE Trans. on Microwave Theory and Techniques 50(5):1-5.

Neitola M & Rahkonen T (2002) Study of fully digital error correction in multibit delta-sigma A/D converters. IEEE Int. Symp. on Circuits and Systems (ISCAS), Phoenix, Arizona, USA, May 26-29, 2: 624-627.

Heiskanen A & Rahkonen T (2002) 5th order multi-tone Volterra simulator with component-wise output. IEEE Int. Symp. on Circuits and Systems (ISCAS), Phoenix, Arizona, USA, May 26-29, 3: 591-594.

Vuolevi J, Aikio J & Rahkonen T (2002) Extraction of a polynomial LDMOS model for distortion simulations using small-signal s-parameter measurements. IEEE MTT-S International Microwave Symposium, Seattle, Washington, June 2-7, 2157-2160.

Lasanen K, Räisänen-Ruotsalainen E & Kostamovaara J (2002) A 1-V, self adjusting, 5-MHz CMOS RC-oscillator. Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, Phoenix, Arizona, USA, May, 4:377-380.

Vuolevi J & Rahkonen T (2003) Distortion in RF power amplifiers, Artech House.