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Circuits and Systems (CAS-Oulu)

Professor Juha Kostamovaara and Professor Timo Rahkonen,
Electronics Laboratory, Department of Electrical and Information Engineering, University of Oulu,

Background and Mission

The Circuits and Systems group consists of about 40 researchers working at the Electronics Laboratory of the Department of Electrical Engineering at the University of Oulu. Its main activity is in the field of electronic and optoelectronic circuit and system design. The primary implementations are based on various ASIC technologies. The main interest of the group is devoted to certain novel circuit topologies and functional units, although the group is also interested in applications, especially in the field of telecommunications and electronic/optoelectronic measurements.

The group's work concentrates especially on the development of high speed electronic (analogue, mixed mode and optoelectronic) circuits and systems. The main research fields are:

  • time-to-digital and digital-to-time converters, i.e. time interval measurement devices and controllable delay generators
  • timing discriminators, especially optical receivers, and detection of the timing of the received optical pulse, including the realization of the optical detector (single element, mosaic, position sensitive) in standard CMOS/BiCMOS technologies
  • picosecond laser diode transmitters and high-speed, high-current switches
  • development of laser radar techniques, especially for industrial measurements, using the results of the above research activities
  • frequency synthesis with the emphasis on the ΔΣ frequency synthesis method
  • radio receivers and receiver architectures based on selective (filtering) sampling techniques
  • radio telecommunications including linearization of power amplifiers, AD/DA conversion and baseband blocks
  • low power/low voltage analogue and mixed-mode signal processing blocks and their integrated circuit realizations, e.g. for biomedical applications.

The group has created a well-functioning partnership with some international research units working in the same or in a complementary field. The primary partners are the University of Lund in Sweden (a shared NorFa network on Terahertz techniques), the University of Kassel in Germany (a shared INTAS project) and the A. F. Ioffe Institute in St. Petersburg (a shared INTAS project). The group is mainly funded by the Academy of Finland, TEKES and industry. It has two graduate school positions from the GETA and three from the Infotech Oulu graduate schools.

Scientific Progress

In the following, some details and results of the work of the group are given in some important research fields.

Laser radars and the related circuits

Time-to-digital conversion

A high precision CMOS-time-to-digital converter was developed, which measures time periods in the picoseconds region. A new delay line structure was developed to enable the use of low external reference frequency and yet to achieve high single shot precision. The idea used was to recycle the external reference oscillator signal in a delay line many times before a new reference signal arrives. The most dominating factor which decreases the single-shot precision in time interval measurements is the systematic nonlinearity of interpolators which does not change when the coincidental phase noise of the reference grows. One can, therefore, increase the noise with the recycling mechanism without reducing the single-shot precision. The critical delay line characteristics such as the length of the time interval, deviation and power consumption were also improved by using a differential delay line structure.

The designed time-to-digital converter was fabricated in 0.35 µm CMOS-technology. The correct operation of the reference recycling technique could not been verified because of a design error, but the performance of the converter was solved by using a full 145 MHz clock frequency. The power consumption with a 3.3 V operating voltage was 55 mW. Measurements show that the rms single-shot precision in room temperature is about 13 ps, which is the best among the known published time-to-digital converters made with CMOS-technology. Temperature drift is below 0.05 ps/°C. The linearity error when measuring different time intervals is less than ±6 ps when the time interval is longer than 12 ns.

Timing detection

A new receiver channel topology for a pulsed time-of-flight laser range finder was developed. The aim of this technique was to enable distance measurement within a wide dynamic range of the received echo, and to achieve millimetre-level accuracy without using automatic gain control (AGC). In the implemented solution, a photo diode gives a unipolar current pulse that is first buffered using a regulated cascade (RGC) coupled current buffer and then converted to a bipolar voltage signal at the input of the receiver channel. The RC network is used to find the timing point. This results in a bipolar signal with a zero-crossing point that is insensitive to the amplitude changes over a large dynamic range, even if the signal saturates the receiver channel, provided that the subsequent gain stages recover rapidly from the saturation. Because of using the RGC current buffer between the diode and the timing detection, problems in signal derivation caused by the diode's parasitic capacitance will be avoided. There is also no need for any off-chip components.

For the designed integrated receiver, simulations showed that the channel input dynamic range is 1:2500 with the corresponding timing accuracy of 70 ps. The receiver IC was fabricated using a 0.35 SiGe BiCMOS and the measurements are in the process.

Unipolar-to-bipolar conversion based timing detection circuitry at the input of the receiver with the typical signal waveforms.

An integrated laser radar chip

A CMOS laser radar chip including two different optical receiver channels and a time to digital converter (TDC) integrated onto the same die has been designed. The die has been fabricated using 0.18 µm CMOS technology. The laser radar chip has two receiver channels based on different timing discrimination strategies. The TDC is based on a temperature and supply voltage stable multiphase ring oscillator without any off-chip reference. The idea was to lock the ring oscillator to an integrated stable voltage reference by frequency to voltage conversion. The receiver part of the chip is estimated to give a timing discrimination accuracy of better than 200 ps in a dynamic range of more than 1:1000. The minimum detectable signal pulse current is around 1 µA.

Picosecond laser pulse generation and high speed switches

A mechanism of field-assisted gain control, which has allowed the generation of 50 W / 20 ps optical pulses, using a specific type of laser diode, was investigated. This mechanism consists of effective gain control by the transverse electric field. The main efforts at the current stage of the research were concentrated on the study of the conditions which are necessary for the mechanism of the gain control to be realised. It was lately found that the efficiency of internal optical pumping intrinsic of this laser diode structure has to be properly optimized, otherwise high-power picosecond laser mode does not manifest itself. It has been experimentally shown that no short-pulsing mode can be obtained with too high efficiency of the internal optical pumping and only quasisteady-state lasing (a) manifests itself. Conversely, at too low a pumping efficiency no lasing occurs at all, and only an optimal pumping efficiency allows the field-assisted gain control to be realised and ps laser kinetics (b) to be achieved. Very important is a recent finding that together with obvious geometrical factor and spectral overlapping, the efficiency of the optical pumping is essentially controlled by the competition between the superluminescent and purely spontaneous mode in the pumping source layer. We have demonstrated that the optical pumping of the active layer is provided by the spontaneous emission of a broad spectrum and spherical angular distribution generated in the source layer, while the presence of the superluminescent mode with a narrow spectrum and confined optical field reduces the pumping efficiency due to the reduction in the spontaneous emission intensity. In practice this finding means that proper designing of a high-power ps laser diode requires careful control of all the parameters, affecting the intensity of the superluminescent mode in the pumping source layer. This novel laser diode structure is currently under international patenting by the University of Oulu.

Pumping current pulse, optical response and time-resolved spectra measured using a streak-camera. (a) corresponds to a case of too high efficiency of internal optical pumping, while a certain reduction in the pumping efficiency causes switching from quasi steady-state (a) to ps lasing modes (b) The efficiency of the optical pumping in the example shown in (b) is not yet optimal, so the power in the picosecond modes (HEM and MEM) remains still on a moderate level. At too low efficiency of optical pumping no lasing would occur.

A related topic is research in the area of high-speed current and voltage switching for the fast pumping of various laser diodes (including the ps laser discussed above), as well as for various sub-nanosecond and ps-range electrical and optical shutters, UWB radars and communications, etc. Fairly impressive results have lately been achieved in the course of the experimental investigation of the switching transient in especially designed and fabricated GaAs avalanche transistors.

A large difference in the electron and hole mobilities would be expected to determine (according to 2D simulations with a drift-diffusion model, "Atlas" device simulator) acceleration in the switching transient by a factor of 1.5 to 2 with respect to the Si transistor, while the experiment has shown an increase in the switching speed by a factor of ~15. This superfast switching cannot be explained by ordinary drift-diffusion modeling.


Left: Experimental and simulated voltage and current waveforms across a GaAs transistor; the experimental data for an Si transistor are shown for the sake of comparison.

Right: Emission patterns corresponding to a single switching of GaAs avalanche transistor at various magnifications: the transient filaments manifest themselves.

A fairly original physical interpretation of the phenomenon was found to originate from the generation and spread along the switching channels of a comb of avalanching Gunn domains of ultra-high amplitude. These domains cause fairly homogeneous and extremely powerful carrier generation along the whole length of the switching channel. An increase in the carrier density reduces drastically the width of the domains, thus reducing the voltage across the device, while the domain amplitude remains extremely high (by a factor of 2 to 3 higher than the ionization threshold), thus supporting a powerful ionization rate even at a reduced voltage across the transistor. This train of Gunn domains with quite unusual parameters appears due to the presence of negative differential mobility (NDM) at extremely high (ionizing) electric fields (which has not typically been taken into account in a large number of publications where the Gunn effect is analyzed); also the current filamentation is a factor of major importance in the phenomenon in question. Excellent agreement was found between the experimental data and the results of the simulations performed with a specifically developed simulation code.

(a) Measured and simulated voltage and current across a GaAs avalanche transistor, (b) Simulated electric field profiles at various instants across the structure (along the switching channels in the direction of the current flux); the instants shown in (b) correspond to the time scale in (a).

The unique switching parameters found for the newly designed semiconductor switch are caused by a completely original physical mechanism responsible for the switching. While in various bipolar structures the speed of the conductivity modulation in the switching region is limited by the drift-diffusion carrier transport, in the device discussed here, the impact carrier generation at an extremely high rate occurs simultaneously and practically homogeneously across the whole switching volume, so that the carrier transport does not limit the switching speed. It is the first time such a switching mechanism has been reported for a semiconductor device. A picosecond-range high-voltage, high-current switch may find various new applications in semiconductor electronics and optoelectronics.

Frequency synthesis

The effect of nonlinearities on the in-band noise of a ΔΣ synthesizer

In the field of synthesis, much of the theoretical work carried out in the group was devoted to how various factors contribute to the Banerjee Figure of Merit (BFM) which is a good measure of synthesizer performance for in-band noise. A theory has been developed on how jitter in digital logic, charge-pump current noise, offset current noise and reference noise contribute to the in-band noise of the synthesizer. Moreover, it has been shown both analytically and experimentally how the nonlinearities of particularly the phase detector mix the high frequency quantization noise peculiar to ΔΣ frequency synthesizers into its in-band noise. In addition, several circuit techniques have been developed and realized by which the above noise sources or their effects can be minimized. To serve as a base for further work, and to validate theoretical understanding of ΔΣ synthesizers, a state of the art prototype was developed.

Avoiding spurs in DS synthesizers by periodical behavioural analysis

The ΔΣ modulator is one of the key units of the fractional-N synthesizer. The synthesized frequency is a product of a stable reference frequency and a fractional number provided by the ΔΣ modulator. However, it is not just a plain, static number. In fact, the modulator generates a sophisticated control signal with the mean corresponding to the desired fractional number. The spectral purity of the ΔΣ modulator generated signal directly affects the spectral purity of the synthesized channel. Therefore first and foremost, the modulator generated signal should be properly noise shaped and free from spurious tones.

Short limit cycles are identified as the most severe cause of spurious tones appearing in the modulator generated signal. In the work of the group, the problem of limit cycles has been eliminated for two common modulator architectures used in fractional-N frequency synthesis. The approach is based on the observation that the modulator sequence length can be controlled for all channels by applying predefined initial conditions and modulator scaling. Long sequences guarantee that the quantization noise does not concentrate on a few dominant spurious tones. At the same time, the modulator behaves in a fully predictable way.

The design method developed allows a quick modulator design for a fractional-N synthesizer. Modulator SRF is easily determined and reliable. A trade-off between the SFR requirement and modulator resolution allows planned and reasonable use of hardware resources.

New ΔΣ architectures

A new ΔΣ synthesizer architecture where phase quantization noise is reduced by utilizing a fractional-N divider, instead of the integer-N divider typically used in ΔΣ synthesizers, has been developed. In the already published system, the VCO cycle fraction was intended to be produced by a delay line, but recent results suggest higher performance when unit element charge pump structures are being used to achieve the same effect. The reason for the improved performance comes from the fact that in the latter realization the mismatch error between the unit element charge pumps will be noise-shaped, whereas in the delay element realization it is only randomized.

The other goal of the group, within this field, has been the digitalization of the whole PLL loop (expect the VCO) by measuring the VCO frequency with a frequency discriminator, or by digitizing the phase difference of the reference source and VCO by accurate time-to-digital converter techniques. One advantage of the digitalization is the flexibility achieved in the design of the loop filter, for example.

Sampling filters

The work in this particular field has concentrated on investigating sub-sampling (i.e. band-pass sampling) with integrated signal processing, such as partial channel selection and anti-aliasing filtering, as a potential alternative for signal conditioning and down-conversion in radio receivers. The use of a sub-sampling circuit in a receiver chain prior to base-band signal processing and A/D conversion can relieve the bandwidth constraints and minimize the power consumption of the base-band discrete-time circuit blocks by lowering their sampling frequency. However, the use of conventional simple sub-sampling circuits has usually been avoided due to their modest dynamic range, especially noise, performance resulting mainly from the lack of proper anti-aliasing filtering in front of the sampler.

Unlike conventional voltage-mode sampling circuits, the sampler structure investigated in this work is based on integrative sampling of a current, or charge, signal. Integrating current into a sampling capacitor within a determinate time window itself produces a continuous-time sin(x)/x-type low-pass response, which limits the noise (and signal) bandwidth of the sampler. Integrating several charge samples into the sampling capacitor during the output sampling period extends the filtering properties of the sampler to discrete-time finite-impulse-response (FIR) filtering. The figure below shows the principle of a general active-integrator-based charge sampling circuit with an embedded N-tap complex FIR filtering function.

Principle of a general selective sampling circuit.

With an appropriate clock scheme, the sampler circuit above can implement an arbitrary complex FIR filter function, the impulse response of which consists of coefficients restricted to the set {±1,0,±j}. The filter taps can be obtained by, for example, quantizing an arbitrary target impulse response using ΔΣ modulation or the unit-charge sample concept proposed recently by the group. Due to its asymmetric response for positive and negative frequencies, a charge sampling circuit with an integrated complex FIR filter can be utilized in radio receivers for image rejection and quadrature down-conversion in addition to its partial channel selection and anti-aliasing filtering properties. Also with a proper choice of circuit implementation, the proposed sampler can be configured to perform complex filtering and further quadrature down-conversion to base-band or to low-IF for complex (I/Q) IF signals.

Research on Linear RF Power amplifiers

The group has for several years been doing basic research to aid the design of high efficiency linear RF transmitters. This work was continued on the following subtopics.

Detailed distortion analysis techniques

The group has previously developed an in-house Volterra simulator for detailed study of the contributions and cancellation mechanisms that result in the total distortion in an analog circuit. Now the same analysis technique was implemented into a commercial circuit simulator, Aplac, using its procedural command language. The simulation procedure consists of the following steps: first, a harmonic balance nonlinear simulation is run; second, using the voltage and current spectra obtained from the simulation, a polynomial model of the nonlinear I-V and Q-V sources can be fitted; third, using the fitted coefficients of polynomial nonlinearities and the simulated voltage spectra it is possible to calculate all the different contributions and mixing mechanisms that cause a given distortion tone, like IM3, for example.

In the next figure, the magnitudes of the total sum and various contributions of IM3 in an LDMOS transistor are shown. The device has a so-called sweet spot at ID = 320 mA, where the total output IM3 distortion (thick black line) drops to -65 dBc, which is more than 15 dB lower than the highest single contribution K20VH2. It can be seen that the sweet spot is close to the bias point where the cubic nonlinearity K30Vi3 (red) goes to zero, but does not completely align it. This is simply because there are several other causes of IM3, and the sweet spot is actually caused by a cancellation between cubic nonlinearity K30Vi3 and an IM3 term generated by a down-converted second harmonic K20VH2. As the latter is affected by the harmonic matching impedances, also the position and depth of the sweet spot are affected by harmonic impedances, and hence vary with the centre frequency and channel bandwidth.

Magnitudes of various IM3 contributions of an LDMOS drain current, shown as functions of the DC bias current.

Development of high efficiency transmitters

The power efficiency of class A or AB linear amplifiers is modest, or even poor, if the ratio between peak power and average power (the so-called crest factor) is high - this is the case, for example, in multi-carrier transmissions. One way to improve efficiency is to allow weak compression, and cancel the generated nonlinearity using predistortion. For this purpose, a 2 GHz RF predistorter IC was previously designed. It has been now fabricated and preliminarily tested at a lower frequency (1 GHz), and a new test setup is currently under construction. The IC consists of a fifth-order polynomial predistorter and a separate output for the squared envelope baseband output, that will be later experimented for cancelling memory effects.

Ultimate efficiency can be achieved using switching amplifiers, like class E amplifiers, but these cannot repeat amplitude information without a modulated power supply. Towards this aim, the design of a polar or EER (Envelope Elimination and Restoration) type transmitter was started in 2004. In EER, the phase information of a constant-envelope modulated carrier and the rectified amplitude information from the modulated power supply are combined in the amplifier. The delays of these paths need to match over a broad band, as the bandwidths of the phase and magnitude information paths are 3-10 times as wide as the desired signal bandwidth. Hence, the modulation bandwidth of the supply voltage needs to be very wide, and also the input matching of the amplifier needs to be broadband. Further technical problems are caused by the modulation bandwidth of the amplifier itself (limited by the DC biasing scheme) and the heavy AM-PM conversion typical of class E amplifiers.

Error correction in data converters

Previous results and experience of digital error correction techniques have been documented during 2004.

Histogram based adaptation

The static integral nonlinearity (INL) of an A/D converter can be calculated from a measured code density or amplitude histogram, provided that the input amplitude is large enough and the input signal has a continuous amplitude density function. Moreover, it is not necessary to collect the complete histogram, but it suffices to collect only a few bins from both sides of a point where some of the msb bits change their value. With this principle, it is possible measure and update the INL correction coefficients transparently during the actual measurement, without a need for specific test signals or calibration periods. Such an implementation is currently being tested using a commercial successive approximation 16-bit ADC as a test device.

Analysis and modelling of the effects of timing errors

Of all possible errors in AD and DA converters, timing errors are the most difficult to analyse and model. DA converters suffer from timing skew in the switching time of the different bits or segments, and of slew-rate limitation at the output. Both these mechanisms cause a very broadband PPM, PAM, or PWM type modulation in the output. The resulting spurious tones are difficult to analyse, because the errors are so narrow that time-domain modelling of them would require the use of very heavy oversampling. By calculating the spectrum of these timing errors semi-analytically using Fourier integrals it was found that the spectral can be predicted by averaging the errors over one sample duration, summing this averaged sequence to the sample train, and performing normal non-oversampled FFT. Hence, a very effective analysis method can be used and is justified.

Another difficult timing error is the timing skew in time-interleaved AD and DA converters. It causes non-uniform sampling, which creates an error that is proportional to the time derivative of the input signal. Hence, for time-domain modelling a broadband digital differentiator is necessary. In the frequency domain analysis, on the other hand, it suffices to multiply the input spectrum by a frequency response that is a sum of a constant response (due to gain mismatch) and a differentiating response (due to timing error), and shift the resulting spectrum around a proper sub-harmonic of the sampling frequency.

The figure below shows the gains of six parallel and time-interleaved ADCs in the form Gk*exp(-jωΔtk), where Gk and Δtk are the gain and sampling time of the converter k, respectively. It can be seen that the cancellation of image spectra at fs/6...fs*5/6 is dictated by the vector sum of the subconverter gain vectors. Moreover, it is interesting to note that all odd subharmonics (1/6, 3/6, 5/6) are most easily cancelled by guaranteeing good matching with converters that sample half a cycle apart from each other - like pairs 1-4, 2-5, and 3-6. This observation leads to new layout placement rules in implementing heavily time-interleaved systems.

Subharmonic cancellation in an interleaved AD converter shown as a vector sum of individual converter gains and timing Gk*exp(-jωΔtk).

Low voltage/low power analogue circuit techniques

In this field, the main focus has been to develop low voltage, low power circuit blocks and systems for portable applications. One of the most important basic circuit blocks in analogue electronics is the operational amplifier. As the supply voltage and power consumption are lowered, new circuit topologies have to be developed, which combine low voltage operational amplifiers with efficient compensation techniques, otherwise performance degradation occurs. Research in this field has focused mainly on developing new power efficient compensation techniques for two and three stage amplifiers, which are, for example, needed as flat panel drivers, in audio and power control circuitry. Manufactured test chips show that by combining the developed compensation structures with rail-to-rail input and adaptive biasing structures, static power consumption of the amplifier can be greatly reduced, without otherwise affecting factors in the amplifier performance such as amplifier bandwidth.

A low-voltage, low-power signal-processing chip for ECG measurements has also been designed and manufactured. The chip consists of a continuous-time preamplifier, an antialias filter, an 8th-order switched-opamp, switched-capacitor (SO-SC) bandpass filter and an SO-SC-output buffer/amplifier. The necessary bias and crystal oscillator circuits are also included on the chip. In order to reduce common-mode disturbance, the whole signal path is differential. The circuit performs an amplification of 60 dB for a signal band of 8-30 Hz. The sampling frequency for the SC blocks is 1 kHz, which is generated from the integrated 32 kHz crystal oscillator. The whole circuit operates with supply voltages from 1 V to 1.8 V.

The measurement results showed that the circuit performs as expected and it achieves a CMRR of 82 dB and a maximum SNDR of 36.1 dB with 1-V supply voltage. The total current consumption of the chip, including the output buffer, is only 3 μA. Furthermore, the average current consumption of the 8th order bandpass SO-SC filter is very low, since it consumes only about 400 nA, corresponding to 50 nA/pole, which is much less than the current consumption of the SC filters in prior designs. Therefore, the circuit is very suitable for portable ECG measurement applications, like heart rate detectors.

Microphotograph of the signal-processing chip for ECG measurements.

Exploitation of Results

The results of the research have been applied by Nokia Mobile Phones, Nokia Networks, Noptel, Polar Electro, National Semiconductor Finland, Elektrobit, Esju and Aplac, for example, who also have been funding the work.


professors & doctors


graduate students






person years


External Funding



Academy of Finland

518 000

Ministry of Education

161 000


304 000

domestic private

151 000

EU + other international

41 000


1 175 000

Doctoral Theses

Kilpelä A (2004) Pulsed time-of-flight laser range finder techniques for fast, high precision measurement applications. Acta Universitatis Ouluensis C 197.

Mäntyniemi A (2004) An integrated CMOS high-precision time-to-digital converter based on stabilized three-stage delay line interpolation. Acta Universitatis Ouluensis C 210.

Selected Publications

Vainshtein S, Kostamovaara J, Sveshnikov Y, Gurevich S, Kulagina M, Yuferev V, Shestak L & Sverdlov M (2004) Superfast high-current switching of a GaAs avalanche transistor. Electronic Letters 40(1):85-86.

Vainshtein S, Yuferev V & Kostamovaara J (2005) Ultra-high field multiple Gunn domains as the physical reason for superfast (picosecond range) switching of a bipolar GaAs transistor. Journ. Appl. Physics 97(2), 9 p.

Rahkonen T, Aikkila J (2004) Linear phase reconstruction filtering using a hold time longer than one sample period. IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications 51(1):178-181.

Rahkonen T, Korajoki V-P & Tuikkanen T (2004) Polynomial behavioral modelling of switched capacitor amplifiers. Kluwer Academics Journal on Analog Integrated Circuits and Signal Processing 38(1):43-51.

Karvonen S, Riley T & Kostamovaara J (2004) A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR. Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), May 23-26, Vancouver, Canada, vol I, 217-220.

Karvonen S, Riley T, Kurtti S & Kostamovaara J (2004) A 50-MHz BiCMOS quadrature charge sampler and complex bandpass SC filter for narrowband applications. Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), May 23-26, Vancouver, Canada, vol. I, 437-440.

Lasanen K & Kostamovaara J (2004) 1-V CMOS preprocessing chip for ECG measurements. Proceedings of the IEEE International Workshop on Biomedical Circuits & Systems, December 1-3, Singapore, 4p.

Nissinen J & Kostamovaara J (2004) Wide dynamic range CMOS receivers for a pulsed time-of-flight laser rangefinder. Proceedings of the IEEE Instrumentation and Measurement Technology Conference IMTC2004, May 18-20, Como, Italy, vol. II, 1224-1227.

Nissinen I & Kostamovaara J (2004) A low voltage CMOS constant current-voltage reference circuit. Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), May 23-26, Vancouver, Canada, vol. I, 318-384.

Nissinen I & Kostamovaara J (2004) A temperature stabilized CMOS ring oscillator for a time-to-digital converter of a laser radar. Proceedings of the IEEE Instrumentation and Measurement Technology Conference IMTC2004, May 18-20, Como, Italy, vol. III, 2342-2345.

Borkowski M & Kostamovaara J (2004) Post modulator filtering in delta-sigma fractional-N frequency synthesis. Proceedings of the 47th Midwest Symposium on Circuits and Systems, July 25-28, Hiroshima, Japan, 325-328.

Pehkonen J & Kostamovaara J (2004) Integrated laser radar receiver with resonance-based timing discrimination. Proceeding of The 30th European Solid-State Circuits Conference, September 21-23, Leuven, Belgium, 427-430.

Vainshtein S, Kostamovaara J, Backman S, Sverlov M & Shestak L (2004) Effect of internal optical pumping on the picosecond kinetics of a laser diode with field-assisted gain control. Proceedings of SPIE Seminconductor Lasers and Laser Dynamics, April 27-30, Strasbourg, France, vol. 5452, 553-561.

Vainshtein S, Yuferev V & Kostamovaara J (2004) Picosecond range switching of a GaAs avalanche transistor due to bulk carrier generation by avalanching Gunn domains. Proceedings of SPIE Ultrafast Phenomena in Semiconductors and Nanostructure Materials VIII, January, San Jose, USA, 382-393.

Aikio J & Rahkonen T (2004) Fitting of a 2-dimensional polynomial model based on simulated voltage and current spectra. IEEE International Symposium on Circuit and Systems ISCAS'04, May 23-26, Vancouver, Canada, vol. 4, 645-648.

Heiskanen A & Rahkonen T (2004) On the second harmonic control requirements in balanced common-emitter BJT low noise amplifier. IEEE International Symposium on Circuit and Systems ISCAS'04, May 23-26, Vancouver, Canada, vol. 1, 833-836.

Rahkonen T & Kortekangas J (2004) Mixed-mode parameter analysis of fully differential circuits. IEEE International Symposium on Circuit and Systems ISCAS'04, May 23-26, Vancouver, Canada, vol. 1, 269-272.