Circuits and Systems (CAS-Oulu)

Professor Juha Kostamovaara and Professor Timo Rahkonen,
Electronics Laboratory, Department of Electrical and Information Engineering, University of Oulu
juha.kostamovaara(at)ee.oulu.fi, timo.rahkonen(at)ee.oulu.fi

http://www.infotech.oulu.fi/cas

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Background and Mission

The Circuits and Systems group consists of about 30 researchers working at the Electronics Laboratory of the Department of Electrical Engineering at the University of Oulu. Its main activity is in the field of electronic and optoelectronic circuit and system design. The primary implementations are based on various ASIC technologies. The main interest of the group is devoted to certain novel circuit topologies and functional units, although the group is also interested in applications especially in the field of telecommunications and electronic/optoelectronic measurements.

The group’s work concentrates especially on the development of high speed electronic (analogue, mixed mode and optoelectronic) circuits and systems. The main research fields are:

• time-to-digital and digital-to-time converters, i.e. time interval measurement devices and controllable delay generators
• timing discriminators, especially optical receivers and timing detection of the received optical pulse
• picosecond laser diode transmitters and high-speed, high-current switches
• development of an all-electronic, room temperature THz radiation source
• development of laser radar techniques, especially for industrial measurements, using the results of the above research activities
• frequency synthesis with the emphasis on the DS frequency synthesis method
• radio receivers and receiver architectures based on selective (filtering) sampling techniques
• radio telecommunications including linearization of power amplifiers, AD/DA conversion and baseband blocks
• low power/low voltage analogue and mixed-mode signal processing blocks and their integrated circuit realizations.

The group has created a well-functioning partnership with some international research units working in the same or in a complementary field. The primary partner is the A. F. Ioffe Institute in St. Petersburg. The group is mainly funded by the Academy of Finland, TEKES and industry. It has one graduate school positions from GETA and two from Infotech Oulu.

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Scientific Progress

In the following, some details and results of the work of the group are given with reference to important research fields.

High speed integrated circuits and devices

Time-to-digital conversion based on delay line interpolation

A CMOS time-to-digital converter, which should measure time intervals with better than 10 ps precision, has been designed and realized in a 0.35 µm CMOS process. Measurements of the circuit are not yet ready, but its architecture and layout are shown in figures below. The new design attempts to improve the linearity of its internal time delays which makes the time measurement more accurate. The time digitizer should also work without any external calibration.

The time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. High resolution (below 10ps) time interpolation within a low frequency (~2 MHz) reference clock cycle time is achieved by combining several techniques. Reference clock cycle time is first divided to over 1000 pieces in a recycling delay line structure. The reference signal circulates over 100 rounds in the differential 6-element delay line before a new jitter-free edge from the reference clock enters the delay line. High resolution interpolation is performed with a load capacitor scaled parallel delay line structure. It divides one delay of the recycling delay line to 36 pieces. A parallel structure of similar delay elements, each containing different load capacitance makes delay differences of below 10 ps possible.

Time-to-digital converter (TDC) architecture utilizing a new interpolation technique was also developed. The measurement is based on a synchronous counter and asynchronous two-stage stabilized delay line interpolation. The first (coarse) interpolation is based on sampling the state of a delay-locked delay line with the hit signals (start and stop). The hit signals are also synchronized to the multiphase clock signals propagating in the delay line. This time-interleaved multiphase synchronization generates a residue for the second (fine) interpolation as if the synchronizing was done with a GHz-level clock signal. The fine interpolation is based on a new cyclic time domain successive approximation (CTDSA) method. The delay difference between the asynchronous hit signal and the synchronized reference signal from the multiphase synchronizer, i.e. the residue for the fine interpolation, is iterated in a cyclic manner one bit at a time, as opposed to the previous art iterating the result LSB by LSB. Therefore, the conversion time of the fine interpolator is constant and much shorter than with the previous cyclic principles. The offset inherent to the synchronization principle used for generating the residue for the fine interpolation is compensated for by having an additional bit in the fine interpolation, i.e. the dynamic range of the fine interpolation equals the delay of two delay cells of the coarse interpolator. This eliminates the need for accurately adjusting the offsets of the asynchronous and synchronous signals of the fine residue, as opposed to the previous TDC implementations utilizing the multistage interpolation principle. Furthermore, no initial calibration of the offsets is needed. The conversion time is a bit longer than that of an interpolator based on a flash principle, but the reduced hardware complexity and a larger dynamic range compensating for the synchronization offset and better achievable LSB resolution make it practicable.

The design specification for the new TDC is as follows: a 32-bin delay-locked delay line is locked to the cycle of a ~100 MHz reference oscillator providing a resolution of ~312 ps for the coarse interpolation. The residue for the fine interpolation is resolved with a 9-bit fine interpolator with 8-bit effective resolution. The combined interpolation ratio, i.e. how many fractions the clock cycle can be digitized to, is 8192 which leads to a nominal LSB resolution of ~1 ps with 100 MHz reference clock and sets the rms quantization noise level to ~0.5 ps in time interval measurement.

Timing detection

A new receiver channel topology for a pulsed time-of-flight laser range finder was developed. The aim of this technique was to enable distance measurement within a wide dynamic range of the received echo and to achieve millimeter-level accuracy without using automatic gain control (AGC). In the implemented solution, a photo diode gives a unipolar current pulse that is first buffered using a regulated cascade (RGC) coupled current buffer and then converted to a bipolar voltage signal at the input of the receiver channel. An RC network is used to find the timing point. This results in a bipolar signal whose zero-crossing point is insensitive to the amplitude changes over a large dynamic range even if the signal saturates the receiver channel, provided that the subsequent gain stages recover rapidly from the saturation. Because of using the RGC-current buffer between the diode and the timing detection, problems in signal derivation caused by the diode’s parasitic capacitance will be avoided. There is also no need for any off-chip components.

The first receiver channel IC was fabricated in 0.35 µm SiGe BiCMOS-technology. The operation voltage of 3.3 V was used. The receiver channel measurements showed that the input dynamic range was ~ 1:2000 with the corresponding timing accuracy of ~ ±55 ps.

The new receiver channel based on the same timing discrimination principle was also realized with the same technology. In the new receiver channel, both the stop and the start channel were fabricated on IC. The timing point drift with a temperature of 1.33 ps/ºC was achieved. Another notable difference to the first channel is that the operation voltage of 5 V was used in the RGC current buffer, whereas the rest of the channel used 3.3 V. Based on the measurements, the input dynamic range was ~ 1:2800 with the minimum signal of 1.34 µA (SNR =10). An accuracy of ~ ±54 ps was achieved (corresponds to ±7.5 mm in distance).

Integrated laser radar chip

A CMOS laser radar chip including an optical receiver channel and a time to digital converter (TDC) integrated onto the same die is under development for 0.13 µm CMOS technology.

The receiver channel uses a leading edge detection, which makes it possible to achieve a wide dynamic range. A disadvantage of the leading edge detection is the walk error induced by the finite rise time of the laser pulse and bandwidth of the receiver. Without any compensation, the walk error can be larger than a couple of nanoseconds. The amount of walk error can be predicted if the amplitude or the rise time of the timing pulse is known. The former method can be used only when the pulse is in a linear range of the channel. In that case, the residual walk error can be quite large. In this new receiver channel, walk error is compensated for by measuring the rise time of the pulse. The compensation range is much wider because measuring the rise time can be continued even if the pulse is saturated. TDC integrated into the same chip is used to measure the rise time of the pulse. Simulation has shown that under ±50 ps walk error can be achieved on 1:10000 dynamic range. The bandwidth and the transimpedance of the receiver channel is about 220 MHz and 100 kΩ, respectively.

The TDC is based on a temperature and supply voltage stable multiphase ring oscillator shown in the figure below. The ring oscillator (VCO) is stabilized by measuring its frequency using a frequency-to-voltage converter (FVC) and locking its output to a stable, digitally controlled voltage reference (V&I REFERENCE). The time-to-digital conversion is based on counting the pulses of this six-stage, differential ring oscillator and additionally registering the state of its 12 phases at the arrival moment of the timing signals (START and STOP) and delayed timing signals (START_del and STOP_del). The resolution of the TDC is derived by dividing the period of the ring oscillator by the number of its phases (12) and the number of the timing signals (2) giving the resolution of 61 ps. The measured temperature dependence of the TDC is less than 0.34% in the temperature range of 0 °C to 70 °C, corresponding to 34 mm in the distance of 10 m. The single-shot precision standard deviation value of the TDC is less than 46 ps (7 mm) in the distance range of 0 to 12 m, and the power consumption is less than 18 mW.

Superfast high-voltage switch based on a GaAs BJT structure

Interesting new results have lately been achieved in the course of experimental and theoretical investigation of the switching transient in specially designed and fabricated GaAs avalanche transistors. Superfast (~200 ps) switching transient was experimentally observed and an original physical interpretation of the phenomenon was suggested. The superfast switching originates from the switching channel of a comb of moving and avalanching field domains of ultra-high amplitude. These domains cause fairly homogeneous and extremely powerful carrier generation along the whole length of the switching channel. Increase in the carrier density causes drastic reduction (“collapsing”) in the domain width, thus reducing the voltage across the device, while the domain amplitude remains extremely high (by a factor of 2 to 3 higher than the ionization threshold) thus supporting powerful ionization rate even at a reduced voltage across the transistor. This train of the collapsing domains appears due to the presence of negative differential mobility (NDM) in extremely high (ionizing) electric fields. Another feature of the process is current filamentation, which is caused by the collapsing domain appearance and supports in turn fast transient development. Excellent agreement was found between the experimental data and the results of the simulations performed with the developed simulation code.

A possibility for further acceleration in the switching transient and significant reduction in the residual voltage was predicted in our latest simulations for a modified geometry of a GaAs transistor chip. These practically important results are currently in the stage of experimental verification.

A prototype of a GaAs avalanche transistor was used for the pumping of commercial laser diodes operating in the gain-switching mode. The generated electrical pulses of 2-10 A in amplitude with the duration in a picosecond and sub-nanosecond range allowed optical pulses of 5 W / 40 ps or, alternatively, 45 W / 70 ps to be obtained using commercial laser diodes consisting of one chip (75 µm in width) or three chips (250 µm in width), respectively. The obtained optical pulses are fairly promising for their utilization in high-precision laser radars. Furthermore, detailed investigations of the carrier dynamics in the gain-switched laser diodes have shown a possibility for further significant increment in the achievable optical power in a modified laser diode structure.

THz emitter based on a GaAs BJT structure

Another very promising application for the avalanche switching mode in GaAs BJT is the generation of pulsed broad-band terahertz emission. Very optimistic predictions were obtained in the preliminary simulations performed for a "high-voltage" (~300 V) transistor (analogous to that used for picosecond-range switching).

Proper designing of the transistor chip for THz emission applications should result in drastic improvement in the coupling between the emitting channels and free space for the total emission band of 100 GHz - 3 THz. The simulations predict for the “standard” transistor as high power as ~100 mW in the band 100 GHz < f < 1 THz, and the same value in the band 1 THz < f < 3 THz , while for the modified structure, the power in each of these bands is an order of magnitude higher (~1 W!). This gives serious grounds for believing that a compact, high-power THz source can be developed on the basis of GaAs BJT.

The chip used in the preliminary experiment was designed for electrical switching operation (not as a THz emitter), and the top ohmic contacts mask very efficiently the bolometer window from the emission source. This means that in the preliminary experiment, we have collected only a very small portion of THz radiation emitted by the switching channels, and the emission in the band 1 THz < f < 3 THz is suppressed.

Digital delta-sigma modulation in radio frequency synthesis

The work in this field has been focused on the modelling and design of digital delta-sigma modulators (DSM) for fractional-N frequency synthesis. Delta-sigma modulators are known for generating undesired, spurious tones, particularly when operating with slowly varying or DC inputs. Radio applications do not tolerate spurious tonal distortions, yet require compact digital implementations in order to save space and power consumption. In compact, digital fixed point implementations problems related to tonal behaviour become even more apparent.

In the course of the work, a modelling method has been developed which predicts the tonal behaviour of DSM with the most troublesome DC inputs. Such analysis becomes possible, particularly when modulators are finite-state machines implemented in fixed-point arithmetic. The model relates the DSM bus width to the number of tones, tone spacing and the average level of tones. This is an important relationship because it effectively shows how much hardware resources are necessary to obtain the desired quality spectrum. Digital DSMs are frequently over-designed to bring the tones beyond detection levels; now with the proposed modelling method, the DSM can be tailored for particular telecommunication requirements, consume less power and occupy less space. The figure below shows a magnified DSM spectrum. The theoretical model correctly predicts measured tone spacing and the average level of the tones.

The proposed method has been used to find conditions when DSM produces a smooth spectrum, free from spurious tones; see the figure below. The approach based on the periodical behavior analysis has been thoroughly compared to dithering, another DSM design method providing good spurious-free performance. The comparison has shown that our method provides as good results as the best dithering method, while requiring less hardware resources. Recently our empirical sequence length prediction algorithms have been confirmed analytically by an independent research group from University College Cork in Ireland.

The proposed method proves particularly useful in optimizing DSM topologies for exact frequency synthesis. Frequency source, even with minimal frequency offset, results in constantly accumulating phase error, which is undesired in some communication standards, including optical networks. Traditionally, a desired frequency is generated with finite accuracy related to DSM bus width in binary fixed point implementation. Generating exact frequencies requires implementing DSM with a different, non binary modulus. Variable modulus arithmetic is an additional hardware cost for DSM implementation. The proposed DSM design and analysis method proves very useful in the arbitrary modulus implementations, as it allows precise estimation of the DSM size to match the telecommunication standard requirements. In the course of the study, a new DSM topology has been invented which allows hardware efficient implementation of arbitrary-modulus arithmetic.

Voltage-to-current converters

Work in this research area has concentrated on investigating the design of such voltage-to-current converter (VIC) topologies that possess both high linearity and bandwidth, and are able to produce good performance also with low-voltage, mixed-signal CMOS-process, where many of those properties of CMOS-transistors that are essential for good analogue performance are sacrificed to facilitate high-speed and low power consumption of digital circuitry. The interest for studied circuits rises, for example, from the possibility to use them as a part of such sub-sampling receiver structures in which RF-signal is processed in current domain in such a way, that some key requirements, such as low noise figure and high image rejection, are met with a structure, whose requirements for semiconductor process are well in line with those set by the digital circuitry that is now embedded into high-performance radio receivers in massive quantities and whose optimization thus tends to dictate the process selection.

Besides noise level, current-mode sub-sampling receiver structures set tight requirements on the linearity of needed g_m-element. The high linearity and bandwidth of the V-I conversion topologies studied here are achieved by means of a highly linear, low-gain current mode feedback loop. An example for a topology in which such an approach for linearity improvement is used is shown in the figure below. Due to the linearity of feedback, only a relatively low amount of gain is needed at the feedback path to produce a substantial reduction in the distortion level. Since the gain is realized in the current domain, the Miller-effect and the resulting enhancement of certain nonlinear capacitive leakage currents that usually limit the performance of high-bandwidth VIC’s are avoided to great extent. Hence the property of the applied feedback principle enables the realization of a very high conversion bandwidth. Apart from high bandwidth, the reliance of operation on current mode feedback also makes it possible to use various distortion cancelling structures.

The topology enables the reduction of the second order distortion currents when the operating range is below 10 MHz by adding a resistor to the feedback loop. Another compensation technique is to cancel the third order intermodulation (IM3) distortion currents by adding a compensating circuit that has the same amplitude as the IM3 distortion current with opposite phase.

To verify the functionality of the current feedback converter topology, two converters with the different kinds of distortion cancellation techniques mentioned above were manufactured in a 0.13 µm BiCMOS process. Also two reference converters without compensating circuits were added to the chip, the layout of which is shown in the figure below. Measurements will be made during spring 2007.

The simulations show, that while an SFDR of ~80 dB can be achieved in a BP-application centered at 100 MHz, the noise integrated from the band 95-105 MHz limits the SINAD to ~70 dB.

Embedded RF testing for telecommunications

The work of the embedded testing research group at the electronics laboratory can roughly be divided into two main branches which deal with different phases of the life cycle testing of electrical products. The first category of projects deals with testing issues encountered during the manufacturing of products. The second group of projects aims to develop techniques and circuit structures needed to implement embedded testing at the system level, and specifically inside integrated circuits. These circuit structures embedded inside the ICs may then be used to test the functionality of the ICs themselves, the surrounding (discrete) electronics and the whole system at any time during the life cycle of the product.

a) Test station – i.e. production testing

The main idea in this group of projects has been the replacement of general-purpose and expensive RF measurement instruments at the test station of the manufacturing line by custom made low-cost measurement instruments. In the two projects shown in the above figure, a simple spectrum analyzer (ABM Apparatus) and a network analyzer (Antenna tester) were developed for the testing of voltage controlled oscillators and for the production testing of mobile phone antennas, respectively. The RF spectrum analyzer developed is, for example, capable of measuring the spectrum of an RF signal up to 3 GHz, and provides output compatible with the IEEE 1149.4 analogue boundary scan standard. The network analyzer developed, with its accompanying software, will allow the testing of multi-band antennas for mobile phones at the factory floor. This device offers an RF magnitude response measurement capability from 600 MHz to 2.7 GHz with high frequency and amplitude precision. The Master’s thesis reporting the development and detailed measurement results with real-life test cases will be finalized within a couple of months.

b) Life cycle testing

In this group, there are two kinds of activities, namely, projects dealing with specific test cases (alternate test of WCDMA transmitter and base station antenna test) and a group of more general projects which forms a continuing effort towards a complete embedded and life cycle testing solution for modern electrical products (IC building blocks). The following paragraphs describe the main efforts during the past year.

Alternate tests form a strong theoretical background, which enables measurements of electrical circuits through secondary measurements. Instead of measuring the desired quantity or property, different (simpler to perform) measurements are made and the final desired result calculated from these so-called alternate measurements. In our work, the specific task is to use alternate test methods in the context of specification (production) testing of WCDMA transmitters. This quite theoretical work may lead to optimized ways of implementing specification testing with a minimum set of simple measurements performed inside the (integrated) WCDMA transmitter circuit. The results of this work will be available during the spring.

The main goal of the base station antenna test project was to implement a system, which could monitor the quality of the cabling between the base station transceiver and the antenna. The capability of a system built around narrow-band time-domain reflectometry in detecting faults (shorts, opens and loose connectors) using an antenna system built out of real-life components was demonstrated and reported in a Master’s thesis.

The major part of the projects shown in the figure above fall under the category of IC building blocks. These projects have developed a number of basic building blocks, which enable the integration of tests as part of IC circuits. These IC blocks provide functions such as virtual probes (switches), IEEE 1149.4-type high-frequency analogue boundary modules (RF-ABM), integrated RF power reference, supply quality and bypass monitoring and built-in test of AD and DA converters. These basic functions serve many of the test needs encountered and mapped during the planning of individual projects. Some of the developed structures have been used to demonstrate the feasibility of embedded testing (RF-ABM IC used to test an I/Q direct modulation RF transmitter).

The REMTEST project (in co-operation with the Optoelectronics and Measurement Techniques Laboratory and the Microelectronics and Materials Physics Laboratories), shown at the bottom of the above figure, gathers together the results and findings of the developed IC building blocks in a real-life context. The aim of this project is to build a real-life demonstration “product” with an embedded test solution built using the developed IC building blocks. This “product” will include an embedded test of a low-frequency analog circuit, an embedded test of RF electronics and embedded testing of a micro computer. The test solution will be built using the IEEE 1149.4 architecture with an embedded (PCB-level) test controller and test equipment (ATE). The project also extends the idea of life cycle testing to the realm of predictive diagnostics of BGA joints and the 1^st implementation of a Universal Test Communication Standard (UTCS) compatible device. Predictive BGA joint diagnostics allows the detection of imminent solder joint failure under a ball grid array –type IC package and the UTCS allows test control and data communication through a network, using a standardized command language currently under development in the Oulu area.

Research on linear RF power amplifiers

The group has for several years been carrying out basic research to aid the design of high efficiency linear RF transmitters. This work was continued on the following subtopics.

Detailed distortion analysis techniques

The group has previously developed two Volterra analysis tools for detailed study of the contributions and cancellation mechanisms that result in total distortion in an analog circuit: an in-house Matlab simulator using user-supplied polynomial models, and a combined model fitting and the Volterra analysis tool implemented on top of harmonic balance simulation and using the command language of a commercial circuit simulator Aplac. Here normal nonlinear device models are used to fit the polynomial models and calculate the various mixing gains from one harmonic band to another. The former is being reported as a Licentiate thesis, the latter as a doctoral thesis.

Janne Aikio’s PhD thesis reports the operation and some example case studies of Volterra analysis on top of harmonic balance simulation. The manuscript was completed at the end of 2006 and sent to pre-examination. Besides the analysis algorithm itself (reported previously in IEEE j. MTT in October 2005), the thesis summarizes the following new results obtained during 2006.

Linearizing an HBT amplifier using 2nd harmonic load pull was experimented using a real implemented amplifier and a passive impedance tuner. After finding an output match with improved linearity, the resulting collector impedance was measured and fed to the Volterra analysis to find out the actual reason for the improvement. The simulated and measured results matched very well. Similarly, the Volterra-on-HB analysis tool was used to study the reasons for AM-PM in the LDMOS power amplifier. Also these simulations were compared to measured data, and the results are reported in Aikio’s doctoral thesis.

During autumn 2006 T. Rahkonen was accepted as a member of FENICS (the First European Network for Industrial Circuit Simulation), a precompetitive consortium of seven industrial companies and seven university groups working on circuit simulator algorithms. The group is now preparing a joint FP7 proposal, where one task is the further development of the Volterra-on-HB analysis.

Development of high efficiency transmitters

The power efficiency of class A or AB linear amplifiers is modest, or even poor, if the ratio between peak power and average power (the so-called crest factor) is high – this is the case in multi-carrier transmissions, for example. There are two main methods for improving the power efficiency of the transmitter: either to allow weak compression and cancel the generated nonlinearity using predistortion, or modulate the power supply according the signal amplitude. Both of these approaches have been tested in practice.

A previously designed 2 GHz RF predistorter IC consisting of a fifth-order polynomial predistorter and low-frequency squared envelope output was tested during autumn 2005. Its measured results were still reported in a conference in January 2006 and in a journal paper that appeared in January 2007. The tests revealed an interesting memory effect caused by a low-frequency resonance in the gate bias circuit of the power linearized power amplifier, reducing the achievable cancellation.

Ultimate efficiency can be achieved using switching amplifiers, like class E amplifiers, but these cannot repeat amplitude information without a modulated power supply. To test a switch-mode amplifier a polar or EER (Envelope Elimination and Restoration) type transmitter was built in a joint project with the Helsinki University of Technology, consisting of a 4-channel 40 MS/s signal generator, a 0.5 W class E amplifier, and broadband modulated power supply. The test setup consists of three important parts shown in the next, the supply modulator, the RF power amplifier, and the digital baseband part. All these blocks are reported as a Master’s thesis and as a Norchip conference paper.

To achieve high efficiency and broadband modulation, a linearly assisted Buck switcher was used for supply modulation. The design was dimensioned by developing a very fast piece-wise linear state-modelling for the system, and it was found that for a high ripple rejection, for example, a very broadband assisting amplifier is needed. The modulator was implemented using off-the-shelf components, and it is capable of delivering a 1 W rectified WCDMA signal to the drain of the RF PA.

The characteristics of the class E PA were studied, and Cgd feed-through from the constant envelope input to the amplitude modulated output was found to be one of the main causes of spectral regrowth. It was also found that AMAM is caused by the limited output current of the switch, and the effects of various package parasitics on the soft-switching operation of a class E amplifier were studied.

Various signal predistortion techniques were tested to improve the signal quality. The feed-through was largely reduced by adding a slight amplitude modulation to the drive signal of the PA, and residual errors were compensated by memoryless polynomial AMAM and AMPM predistortion mapping functions. These helped to improve the ACPR by 20 dB, as shown in the figure below, where the original and two different types of linearization are applied.

During autumn 2006, a linear class AB amplifier was designed and built for testing an envelope tracking (ET) transmitter. These tests were started in January 2007 and will be reported as a Master’s thesis. Here, the main nonideality seems to be the voltage dependent output match of the LDMOS transistor used.

Error correction in data converters

A few years ago, an FPGA-based training circuit for digital error correction of analog-to-digital converters was developed, consisting of a digital sine generator, real-time error calculation and adaptation logic for digital error correction. Now this idea has been modified so that it includes a digital PLL that tracks the analog input signal and generates the ideal reference for error calculation and correction adaptation. The system was implemented on an FPGA and used to linearize a 14-bit, 300 kS/s pipeline AD converter. The setup was functional, and the PLL-based error correction was able to adapt within 0.5 seconds, which is fast enough for production line calibration, for example. As a result of the adaptation the SFDR of the converter improved from ca. 66 dB up to 80 dB at low frequencies, where dynamic nonlinearities are insignificant (the SFDR drops to 72 dB closer to Nyquist frequency). The results of this work were reported at Norchip conference.

M. Neitola completed his Licentiate thesis on the design methods of sigma-delta AD converters and the digital error correction schemes used in multibit sigma-deltas. The thesis was accepted in spring 2006.

A symbolic flow-graph analysis tool has been developed previously, and now it was extended to simplify symbolic transfer functions of multi-stage operational amplifiers. The terms in the transfer function were reduced so that the gain-bandwidth and phase margin of the response were maintained. The developed transfer function reduction tool was reported at the SMACD workshop.

Low voltage/low power analogue circuit techniques

The work in this field has concentrated on developing low power circuit blocks and systems for portable applications. Focus has been on improving class AB amplifier control circuits and power supply noise rejection performance for low-power low-voltage class AB operational amplifiers, which is important when operational amplifiers are operated in a noisy mixed signal environment or directly from a battery.

One example of a developed amplifier topology is shown below. It has considerable 100 mA current output capability; low quiescent current and approximately 20 dB better positive supply noise rejection performance than similar Miller compensated class AB amplifiers. Therefore it can be used, for example, as an AD/DA-converter buffer or as linear audio headphone amplifier.

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Exploitation of Results

Results of the research have been applied by, among others, Nokia Mobile Phones, Nokia Networks, Noptel, and Selmic, who also have been funding the work.

Personnel

professors & doctors	8
graduate students	14
others	15
total	37
person years	27

External Funding

Source	EUR
Academy of Finland	333 000
Ministry of Education	139 000
Tekes	206 000
domestic private	137 000
EU + other international	42 000
total	857 000

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Doctoral Theses

Karvonen S (2006) Charge-domain sampling of high-frequency signals with embedded filtering. Acta Universitatis Ouluensis C233.

Selected Publications

Karvonen S, Riley T & Kostamovaara J (2006) Charge-domain FIR sampler filter with programmable filtering coefficients. IEEE Transactions on Circuits and Systems II 53(3): 192-196.

Karvonen S, Riley T, Kurtti S & Kostamovaara J (2006) A Quadrature charge-domain sampler with embedded FIR and IIR filtering functions. IEEE Journal of Solid-State Circuits 41(2): 507-515.

Pehkonen J, Palojärvi P & Kostamovaara J (2006) Receiver channel with resonance-based timing detection for a laser range finder. IEEE Transactions on Circuits and Systems I 53(3): 569-577.

Jansson J, Mäntyniemi A & Kostamovaara J (2006) A CMOS time-to-digital converter with better than 10 ps single-shot precision. IEEE Journal of Solid-State Circuits 41(6): 1286-1296.

Loikkanen M & Kostamovaara J (2006) Low voltage CMOS power amplifier with rail-to-rail input and output. Analog Integrated Circuits and Signal Processing 46(3): 183-192.

Lanz B, Vainshtein S & Kostamovaara J (2006) High power gain-switched laser diode using a superfast GaAs avalanche transistor for pumping. Applied Physics Letters 89, 081122, 3 p.

Loikkanen M & Kostamovaara J (2006) PSRR Improvement technique for single supply class AB power amplifiers. Electronic Letters 42(25): 1435-1436.

Rapakko H & Kostamovaara J (2006) V-I converter with high linearity and bandwidth. Electronics Letters 42(15): 833-834.

Rahkonen T & Repo H (2006) Efficient behavioral modelling of small timing errors in A/D and D/A converters. Kluwer Academic Journal on Analog Integrated Circuits and Signal Processing 46(1): 29-36.

Vainshtein S & Kostamovaara J (2006) High power gain switched laser diodes using a novel compact picosecond switch based on a GaAs bipolar junction transistor structure for pumping. Proc. of SPIE, V. 6184, 618403/1-9.

Häkkinen J, Hannu J, Manninen J, Syri P & Moilanen M (2006) Embedded high-frequency analogue boundary scan test solution for a 900 MHz direct conversion I/Q transmitter. Proc. of the 2006 International Mixed-Signals Testing Workshop, June 21-23, Edinburgh, UK.

Borkowski M & Kostamovaara J (2006) On randomization of digital delta-sigma modulators with dc inputs. ISCAS 2006, IEEE International Symposium on Circuits and Systems, Kos, Greece, May, 3770-3773.

Rahkonen T, Kursu O, Riikola M, Aikio J & Tuikkanen T (2006) Performance of an integrated 2.1 GHz analog predistorter. 2006 International Workshop on Integrated Nonlinear Microwave and Millimeter-Wave Circuits (INMMIC 2006), January 30-31, Aveiro, Portugal, 34-37.

Aikio J, Vuolevi J & Rahkonen T (2006) Detailed distortion analysis technique based on VBIC model. 1st European Microwave Integrated Circuits Conference (EuMIC 2006), September 10-13, Manchester, UK, 445-448.

Neitola M, Loikkanen M & Rahkonen T (2006) An amplifier transfer function clean-up tool for Matlab. Proc. IX International Workshop on Symbolic Methods and Applications on Circuit Design (SMACD’06), October 12-13, Firenze, Italy, 3 p.

Karttunen J & Rahkonen T (2006) A PLL-based real-time adaptation circuit for digital error correction of a pipeline A/D converter. Norchip conference, November 20-21, Linköping, Sweden, 163-166.

Jokitalo O-P & Rahkonen T (2006) Design of a linearly assisted switcher for a supply modulated RF transmitter. Norchip conference, November 20-21, Linköping, Sweden, 1-4.

Hietakangas S, Rautio T & Rahkonen T (2006) 1 GHz class E RF power amplifier for a polar transmitter. Norchip conference, November 20-21, Linköping, Sweden, 5-10.

Rautio T, Hietakangas S & Rahkonen T (2006) Development environment for EER and envelope tracking RF transmitters. Norchip conference, November 20-21, Linköping, Sweden, 151-153.