Circuits and Systems (CAS-Oulu)

Professor Juha Kostamovaara and Professor Timo Rahkonen,
Electronics Laboratory, Department of Electrical and Information Engineering, University of Oulu

juha.kostamovaara(at)ee.oulu.fi, timo.rahkonen(at)ee.oulu.fi

http://www.infotech.oulu.fi/cas

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Background and Mission

The Circuits and Systems group consists of about 30 researchers working at the Electronics Laboratory of the Department of Electrical and Information Engineering at the University of Oulu. Its main activity is in the field of electronic and optoelectronic circuit and system design. The primary implementations are based on various ASIC technologies. The main interest of the group is devoted to certain novel circuit topologies and functional units, although the group is also interested in applications especially in the field of telecommunications and electronic/optoelectronic measurements.

The main research areas are:

• time-to-digital converters, and timing circuits in general
• radio telecommunications including linearization of power amplifiers, AD/DA conversion and baseband blocks
• breakdown phenomena in semiconductors
• development of pulsed time-of-flight laser range finding techniques, especially for industrial applications

The group has created a well-functioning partnership with international research units working in the same or in a complementary field. The group is mainly funded by the Academy of Finland, Tekes and industry.

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Scientific Progress

In the following, some details and results of the work of the group are given with regard to some of the important research fields.

Time-to-Digital Converters and Timing Circuits

Time to Digital Converter based on Multi-Phase Delay Line Interpolation

An integrated time-to-digital converter circuit was designed with 0.35 µm CMOS technology. The TDC is capable of measuring 0 - 1 ms time intervals with ~10 ps precision, and works with a low ~10 MHz reference clock frequency. The circuit operation is stabilized automatically against process, voltage and temperature variations and it does not need any external adjustment procedures.

The time interval between two timing signals (start and stop) is digitized in the circuit by comparing it to the external reference clock cycle time. A counter records the number of full reference clock cycles between the timing signals, and a two-level (coarse-fine) interpolation architecture solves the location of each timing signal within the reference clock cycle. The architecture of the TDC is presented in the figure below.

 

TDC architecture and the picture of the chip.

 

The first coarse interpolation level creates many small, even length time samples inside each reference clock cycle. This multi-phase clock is created with a new delay locked delay line structure, which makes low reference clock frequency possible and decreases the interpolation nonlinearity compared to the previous traditional DLL-based structures.

The interpolator recycles the reference clock rising edge in a short (a small number of cascaded delay elements) delay line many times during each reference clock period. After N recycling rounds, a new, jitter-free reference edge is transmitted to the delay line and the recycling begins again. The recycling is realized by connecting the end of the delay line to the first element with a multiplexer, as shown in the previous figure. This multiplexer is controlled with a counter, which calculates the recycling rounds. All the delay elements are identical delay adjustable multiplexers so that the delay element propagation delay (τ₁) is constant. A small number of delay elements decreases the integral nonlinearity of the delay line. The reference clock frequency can be decreased simultaneously by increasing the number of recycling rounds N. The cascaded delay elements produce time samples with even time margin (τ₁), when the recycling signal propagates in the delay line. The incoming timing signals (start and stop) record the states of the delay line, and control (enable and disable) the counter, which counts the rounds of the recycling delay line between the timing signals. This interpolation structure with the counter makes long range time interval measurement possible with the resolution of delay element delay τ₁.

Time interval measurement resolution of one delay element unit delay (τ₁≈ 350 ps @ 0.35 µm CMOS) can be achieved with the interpolation structure mentioned above. In order to achieve higher resolution, sub-gate-delay interpolation structures have to be used. The second interpolation level (fine interpolator) interpolates the location of the timing signal within the result of the first interpolation level. The region of the result of the first level (τ₁) is interpolated with ~10 ps resolution by utilizing a parallel load capacitor-scaled delay line structure.

The fine interpolator creates small time differences between the parallel delay elements with load capacitor scaling. The element gate-delay increases linearly with the load capacitance in the output of the element. When several parallel elements include a different amount of capacitive load, a common input signal creates time samples to the element outputs with sub-gate-delay time difference.

The synchronized result from the coarse interpolator (sync-signal) creates the 8 parallel time samples with τ₂ ≈ 10 ps resolution in the previous figure. Simultaneously the delayed, asynchronous timing signal (start or stop) creates 8 time samples with 6τ₂ ≈ 60 ps time difference. The coincidence of these time samples is registered and defines the second interpolation level result.

The measured performance of the developed TDC is presented in the table with a picture of the chip below.

 

 

Developed TDC chip.

 

Time-to-Digital Conversion based on Time Domain Successive Approximation Interpolation

A time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 µs dynamic range was also developed. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method utilizing a pair of digital-to-time converters (DTC), between which the propagation delay difference is implemented by digitally controlling the unit load capacitors of their delay cells. The rms single-shot precision, i.e. standard deviation σ-value of the TDC is 3.2 ps, which is achieved by minimizing the measurement errors caused by the integral nonlinearity (INL) of the interpolators with a correction look-up table (INL-LUT) containing the measured INLs of the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 µm CMOS process.

The figure below shows schematically the operation principle of the time domain successive approximation algorithm for 4 bits, and the second figure shows the corresponding electrical realization for an 8 bit interpolator.

 

Operating principle of a 4-bit CTDSA method as a timing diagram.

 

Realization of an 8-bit CTDSA interpolator.

 

The next figure shows the distribution of a measured single shot with a length of ~100 ns. The precision is 5.7 ps and can be improved down to 3.0 ps if the measured non-linearity of the interpolator is used to correct the individual measurements.

 

Distribution of the single shot measurement results with Tmeas ~100 ns.

 

Laser Radar Receiver Chip

A new receiver channel topology for a pulsed time-of-flight laser range finder has been developed, fabricated and measured. The timing detection is based on leading edge detection in the receiver channel, which makes possible a very wide dynamic region. The receiver channel has been realized in a 0.35 µm SiGe BiCMOS process.

The compensation principle utilizes the time-to-digital converter (TDC) to perform the compensation of the walk error. The walk compensation principle is based on the measurement of the pulse length of the received optical pulse. A simplified block diagram of the receiver channel is shown in the next figure. In the timing comparator, a master-slave type latch has been used for discriminating both the rising and the falling edge of the detected pulse. Thus, as the relation between the measured walk error and pulse length is known through the whole dynamic region the walk error compensation can be made.

 

Block diagram of the integrated laser radar receiver channel.

 

Based on the measurements, the bandwidth and the transimpedance of the receiver channel are 230 MHz and 11 kΩ, respectively. The input referred rms noise current was < 100 nA, thus the minimum signal of ~1 µA is required for the SNR of 10. The maximum measured input current was about 100 mA. Thus the input current varies at the range of 1:100,000. In this dynamic range, the uncompensated walk error was about 1.8 ns while the use of compensation the error was reduced to be less than ±20 ps, as can be seen below.

 

Compensated walk error.

 

Integrated Laser Radar Chip

A CMOS laser radar chip including an optical receiver channel and a time to digital converter (TDC) integrated on to the same die, and realized in a 0.13 µm CMOS technology has been fabricated and tested. A block diagram of the receiver chip for a pulsed TOF laser rangefinder with I/O pads is shown below. The optical pulse is first converted to a current pulse in an external photodetector, and then amplified in a transimpedance preamplifier (Z) and further amplified in a voltage-type postamplifier (A). Two timing comparators with different thresholds, V_th1 and C*V_th1 (generated by DAC1 and DAC2), were used to generate the logic-level timing marks STOP and STOPtr. The TDC has separate channels to measure the START-STOP time interval used to calculate the distance to the target, and the STOP-STOPtr time interval (proportional to the slew rate) used to correct the timing walk error caused by the varying amplitude of the received pulse. This, of course, necessitates the use of a look-up table or a fitting calibration curve which contains time walk information collected during calibration of the receiver. It should be noted, however, that calibration may not be needed for every circuit, depending on the accuracy required. In addition, the receiver chip includes SIPO to program the receiver, a calibration counter (CTR) to compensate the temperature and supply voltage dependences of the TDC, a delay locked loop (DLL) to lock parallel sub-gate-delay elements and a control logic to read the results.

 

Block diagram of the CMOS laser radar chip.

 

A photograph of the receiver is shown below. The size of the layout of the whole receiver, including the pad ring, was 1300 µm x 1300 µm. The operation frequency of the ring oscillator was 1.1 GHz, giving a resolution (LSB) of 14 ps (T_clk/(16*4)) for the TDC corresponding to 2 mm in distance, when the total power consumption of the receiver was approximately 45 mW. The nonlinearity of the TDC was measured to be less than ±7 ps (±1 mm) over the input time range of 5 ns - 100 ns (0.75 m - 15 m).

 

A photograph of the CMOS laser radar chip.

 

The bandwidth and the transimpedance of the channel were 300 MHz and 23 kW, respectively. The input referred rms noise current was 95 nA (C_d = 1.5 pF). The uncompensated walk error was about 2.2 ns in the input current range of 2 µA to 20 mA while the use of the compensation reduced it to less than ±30 ps, as shown in the next figure. The total accuracy of the receiver is better than ±5.5 mm in the distance range of 0.75 m - 15 m including both the nonlinearity of the TDC and the walk error of the receiver channel.

 

Compensated walk error of the CMOS laser radar receiver.

 

The single-shot precision of the whole receiver, including the precision of the TDC is shown next. The worst case single shot precision was 250 ps (~38 mm in distance) at the minimum usable signal corresponding to the SNR of 25.

 

Single-shot precision of the CMOS laser radar receiver in a dynamic range of 1:10 000.

 

Superfast High-Voltage Switch based on a GaAs BJT Structure

Interesting new results have lately been achieved in the course of experimental and theoretical investigation of the switching transient in specially designed and fabricated GaAs avalanche transistors. A superfast (~200 ps) switching transient was observed and an original physical interpretation of the phenomenon was suggested. The superfast switching originates from the switching channel of a comb of moving and avalanching field domains of ultra-high amplitude. These domains cause fairly homogeneous and extremely powerful carrier generation along the whole length of the switching channel. Increase in the carrier density causes drastic reduction ("collapsing") in the domain width, thus reducing the voltage across the device, while the domain amplitude remains extremely high (by a factor of 2 to 3 higher than the ionization threshold) thus supporting a powerful ionization rate even at a reduced voltage across the transistor.

 

(a) Measured and simulated voltage and current across GaAs avalanche transistor; (b) simulated electric field profiles at various instants across the structure (along the switching channels in the direction of the current flux); the instants shown in (b) correspond to the time scale in (a).

 

This train of collapsing domains appears, provided that two non-trivial conditions are satisfied: (i) an active semiconductor layer is biased with an electric field comparable with the ionization threshold (E_i ≈ 2×10⁵ V/cm), and not only at the threshold of the Gunn effect (E_t ≈ 4×10³ V/cm); (ii) negative differential mobility (NDM) takes place not only near the threshold of the Gunn effect, but lasts well beyond the ionization threshold. The electron transport in GaAs beyond the ionization threshold is an open question and existing theoretical data are contradictory. We have performed the work while performing Monte Carlo simulations of the electron transport in an extreme field and its experimental verification in a GaAs BJT operating in avalanche mode.

 

(1-4) Dependence of electron velocity on the electric field in GaAs obtained using analytical-band Monte Carlo model for different doping levels 1015 - 5×1018 cm-3. The gray-colored curves A-C show the change from negative to positive differential mobility predicted earlier with account for X7 valley of the second conduction band. Curve 5 represents our Full Band Monte Carlo simulation results with X7 valley included.

 

Application of data obtained from different Monte Carlo simulations to modelling of the transient in a GaAs avalanche BJT has allowed the conclusion to be made that NDM in GaAs takes place at least up to an electric field of 600 kV/cm, while earlier it was believed that the differential mobility changes its sign from negative to positive already at 350 kV/cm. This result related to the fundamental properties of GaAs is of major importance for various processes in ultra-high electric fields.

 

Measured (curve 1) and simulated (curves 2, A, B, C) collector voltage across a GaAs BJT during switching. The simulation results presented in curve 2 were obtained for the dependence vn(E) represented by curves 1-4 in the previous figure. Curves A, B, C here correspond to the curves in the previous graph marked with the same letters. Curve 3 presents the collector voltage simulated with the dependence vn(E), as shown by curve 5 in the same graph (FBMC results obtained in this work).

 

Picosecond Laser Diodes

A prototype of a GaAs avalanche transistor was used for the pumping of commercial laser diodes operating in the gain-switching mode. The generated electrical pulses of 2-10 A in amplitude with a duration in the sub-nanosecond range allowed optical pulses of 5 W / 40 ps or, alternatively, 45 W / 70 ps to be obtained using commercial laser diodes consisting of one chip (75 µm in width) or three chips (250 µm in width) respectively.

Much more impressive, record power density in the picosecond lasing mode was obtained from a specially designed and fabricated laser diode structure based on heavily doped layers of a GaAs / AlGaAs system.

 

A 50W / 30 ps optical pulse generated near the trailing edge of the pumping current pulse at room temperature. The area of the laser diode chip is 400 µm × 20 µm (length × width). The peak optical power density of ~0.1 GW/cm2 at the mirror is something of a record for picosecond laser diodes.

 

This laser diode can be pumped with a commercial Si avalanche transistor, which makes this result very interesting for applications. Even though Si avalanche transistors have commercially been utilized for many years, we have lately shown that there are 3-D phenomena which affect drastically transistor operation in short-pulsing mode; this has not been previously demonstrated. This work still continues, as the phenomena are not simple and have multiple effects on the operating mode of an avalanche Si transistor.

Very lately we have also found an extremely clear correlation between the breakdown voltages of the p-n junction of an SH laser diode with its addiction to high-power picosecond pulse generation. Namely, gradual p-n junction comprised in an SH structure causes picosecond lasing, while SH structure with an abrupt p-n junction provides quasi-steady-state lasing. Careful verification and practical utilization of this completely unexpected behavior is currently a subject of further study.

THz Emission from a GaAs BJT Structure during Its Avalanche Switching

Another very promising application for the avalanche switching mode in GaAs BJT is the generation of pulsed broadband terahertz emission. Periodical nucleation and annihilation of ultra-narrow, ionizing domains is believed to cause the THz emission observed in our experiment. The measured emission power observed in the BJT operating in pulsed ( ~2 ns) mode was rather high (in the sub-milliwatt range), while even much higher power was predicted in the simulations.

 

(a) Schematic presentation of the transistor chip and experimental setup; (b) oscillograms of Si bolometer responses with different band-pass filters: 1 - f < 0.3 THz (emitted by transistor peak power  ~150 µW); 2 - f < 1 THz (peak power ~100 µW), 3 - f < 9 THz ; 4-f < 25 THz. The signal presented by curves 3 and 4 correspond to black-body radiation, while curves 1 and 2 show the emission from the switching channels; (c) measured (1,2) and simulated (3-5) peak power for a “low voltage” (100 V) transistor; curves 6 - 7 show the simulated emission power in different spectral bands for a “high voltage” (300V) transistor; (6) corresponds to band f < 0.3 THz, (7) to f < 1 THz and (8) to f < 3 THz.

 

This physically interesting and practically promising result requires very careful verification, however, as pulsed, nanosecond-range THz emission was detected as an average sub-THz (THz) signal with a very large (~ 10⁴ - 10⁵) duty cycle. Work is now underway on the installation of a unique high-speed (ns range) bolometer using superconductive nano-scale sensors based on MoRe and NbN, fast (ps range) image intensifier, etc.

Circuit Analysis Techniques and Results

Volterra-on-Harmonic Balance Analysis

To be able to see a detailed construction, dominant causes and cancellation mechanisms of nonlinear distortion in analog circuits, a technique called Volterra-on-Harmonic Balance (VoHB) was developed in J. Aikio's doctoral thesis. Further development of the method has been continued in groups, first in an EU (FP7) project ICESTARS (Integrated Circuit/EM Simulation and design Technologies for Advanced Radio Systems-on-chip), where eight groups are developing circuit simulation and analysis techniques for future mm-band radio circuits.

The ICESTARS project started February 2008, and the following progress has been made. First, a fast numerical convolution algorithm utilizing the symmetry of real spectra was developed to calculate the spectral regrowth effects in polynomial nonlinearities. Second, the numerical properties of polynomial model fitting techniques were studied in detail to find the most reliable way of fitting a 3-D electro-thermal model using just a 2-tone test signal. Third, a prototype of a high-speed harmonic load pull analysis using Volterra analysis was implemented. It fits a polynomial model using one nonlinear HB analysis and then performs a load and source pull for bias and 2^nd harmonic impedances using ac Volterra analysis. The aim of this is to find a matching that results in a distortion minimum. The figure below shows an example where baseband and 2^nd harmonic base and collector impedances of an amplifier are swept over the entire Smith chart. The achieved implementation runs under an interpreter, but is faster by a factor of five compared to fully binary implementation of an harmonic balance.

As a case study of the VoHB technique, the origins of AMPM distortion in an LDMOS amplifier were studied, and was accepted for IEEE Trans. on Microwave Theories and Techniques. The following causes of AMPM conversion were identified:

• the large-signal values of device capacitances vary with an increasing signal, and slightly pull the response of the matching networks. This effect is pronounced, especially with high-Q matching networks
• any nonlinear capacitance automatically generates AMPM, as their distortion products are in 90 degree phase shift compared to the fundamental signal
• down conversion from 2^nd harmonic is typically non-coherent with the fundamental signal and also causes AMPM. Hence, minimization of the 2^nd harmonic helps to reduce AMPM.
• finally, large AMPM is associated to the signal level, where the general shape of the AMAM distortion changes from expansive to compressive behavior

 

IM3 distortion in dBV as a function of harmonic (baseband and 2nd harmonic) input and output matching impedances.

 

Other Research Related to Circuit Analysis

The group has also been working on fast behavioral transient simulations to aid design space exploration of circuits that would be very slow to simulate with transient analysis. Here, linear time-varying state-space models are used to minimize the number of time points needed to solve a given time response. Three case studies were reported during the year: the simulation technique and model of a linearly assisted switcher (reported in the Journal of Analog Integrated Circuits and Signal Processing), the analysis of time skew errors in a time-interleaved D/A converter system (reported in the SCEE conference), and a nonlinear settling modelling of an integrator in a delta-sigma A/D converter using 1-D and 2-D LUTs and a nonlinear state-space model to train these models (also at the SCEE).

 

Effect of 0.1% sample period timing skew in a time-interleaved D/A system, calculated by having only 8 time points per sample.

 

Development of Supply-Modulated RF Transmitters

Switching Amplifiers

During 2007, the group started very informal co-operation with the Technical University of Trondheim, Norway, and it is now bearing results. By the turn of 2007/2008, a 3 W, 1.6 GHz GaAs pHEMT inverted class E switching power amplifier was designed, and then tested during 2008. The main findings were reported in two conference papers. Also an earlier study of a discrete supply modulated class E amplifier was published in the Journal of Analog Circuits and Signal Processing.

Already during the design, it was found that non-overlapping current and voltage waveforms are difficult to achieve in a physically large transistor. A further study showed that the high input drive signal causes huge modulation of the gate capacitance, which results in high 2^nd order distortion that easily alters the duty cycle of the switching transistors. An the InMMIC conference (Integrated Nonlinear Microwave and Millimeter-wave Circuits) a paper described the origins and cancellation techniques of these effects, while the design and general features of the amplifier are described in a Norchip conference paper.

Supply Modulated Transmitters

Previous research on studying different supply drive methods, ET and polar transmitters was published in the Elsevier Journal of Circuit Theory. The research continued by studying the effect of timing misalignment between supply and carrier branches, as well as the effects of various modulation schemes. It was found, for example, that timing skew combined with uncorrected AMPM error results in clear spectral asymmetry. Correct timing is easily found by sweeping the timing until the distortion side-lobes are equal. Then AMAM can be corrected by varying the shape of the supply modulation, and AMPM can be incorporated into the carrier signal.

To improve the measuring capabilities of the group, J. Sandberg has written his Master's thesis which explores all the possibilities offered by the group's 4-port network analyzer FSQ-8. Now the group has documented measurement procedures for measuring conversion gains of mixers, or performing high power sweeps using an external buffer amplifier and directional couplers.

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Personnel

professors & doctors	10
graduate students	18
others	7
total	35
person years	25

External Funding

Source	EUR
Academy of Finland	487 000
Ministry of Education	83 000
Tekes	153 000
domestic private	103 000
international	149 000
total	975 000

 

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Doctoral Theses

Lyöri V (2008) Structural monitoring with fibre-optic sensors using the pulsed time-of-flight method and other measurement techniques, Acta Universitatis Ouluensis C 291.

Borkowski M (2008) Digital Δ-Σ Modulation, variable modulus and tonal behaviour in a fixed-point digital environment, Acta Universitatis Ouluensis C 306.

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Selected Publications

Duan G, Vainshtein S & Kostamovaara J (2008) Lateral current confinement determines silicon avalanche transistor operation in short-pulsing mode. IEEE Transactions on Electron Devices 55(5): 1229-1236.

Lasanen K & Kostamovaara J (2008) 1.2-V CMOS RC oscillator for capacitive and resistive sensor applications. IEEE Transactions on Instrumentation and Measurement 57(12): 2792-2800.

Vainshtein S, Yuferev V, Palankovski V, Ong D-S & Kostamovaara J (2008) Negative differential mobility in GaAs at ultrahigh fields: Comparison between an experiment and simulations. Appl. Phys. Lett. 92, 062114, 3p.

Loikkanen M, Keränen P & Kostamovaara J (2008) Single supply high PSRR class AB amplifier. Electronic Letters 44(2): 70-71.

Hallman L & Kostamovaara J (2008) Effect of signal quantum shot noise on the jitter of leading edge detected and high-pass discriminated laser pulse signals. Measurement Science and Technology 19: 1229-1236.

Jansson J, Mäntyniemi A & Kostamovaara J (2009) Synchronization in a multi-level CMOS time-to-Digital converter. Accepted to be published in IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications.

Nissinen I & Kostamovaara J (2009) On-chip voltage reference-based time-to-digital converter for pulsed time-of-flight laser radar measurements. Accepted to be published in IEEE Transactions on Instrumentation and Measurement.

Kozmin K, Johansson J & Kostamovaara J (2009) A low propagation delay dispersion comparator for a level-crossing AD converter. Accepted to be published in Analog Integrated Circuits and Signal Processing.

Ryvkin B, Avrutin E & Kostamovaara J (2009) Asymmetric-waveguide laser diode for high-power optical pulse generation by gain switching. Accepted for publication in the IEEE/OSA Journal of Lightwave Technology.

Hietakangas S, Rautio T & Rahkonen T (2008) One GHz class E RF power amplifier for a polar transmitter. Analog Integrated Circuits and Signal Processing 54(2): 85-94.

Rahkonen T & Jokitalo O-P (2008) Design of a linearly assisted switcher for a supply modulated RF transmitter. Analog Integrated Circuits and Signal Processing 54(2): 113-119.

Rautio T, Harju H, Hietakangas S & Rahkonen T (2008) Envelope tracking power ampifier with static predistortion linearization. International Journal of Circuit Theory and Applications. Published online August 26 in Wiley InterScience, 11 p.