Description	Specified Value
Technology	0.35 µm CMOS
Resolution LSB	≈ 10 ps
Measurement precision	≈ 8 ps
Measurement range	+/-83.5 ms, equals +/- 12.5 km
Nonlinearity	< ±10 ps (± 1.5 mm)  range < 1 m
Nonlinearity	< ±2 ps (± 0.3 mm)  range >1 m
Temperature drift from start to stop pulse In pulse width measurement	-0.5 ps/°C  (9 mm @ -40 .. 85 °C) -3.0 ps/°C  (50 mm @ -40 .. 85 °C)
External reference	3 MHz - 20 MHz
Internal frequency	≈ 200 MHz typical
Conversion time after last stop	≈ 50 ns
SPI clock frequency max	100 MHz
Timing signal inputs	LVCMOS compatible
Other IO-signals	LVCMOS compatible
Supply voltage	3.3V typical (3.0 – 3.6 V)
Power consumption	≈ 85 mW
Temperature range	-40°C .. 85°C
Circuit size	2.4mm x 3.7mm
Package	QFN 36

 

 

Figure 2. Block diagram and layout of the 6 channel CMOS TDC circuit realization.

 

A Sub-ps-level Resolution Time-to-Digital Converter CMOS Based on Time Domain Successive Approximation Interpolation

A time-to-digital converter (TDC) with sub-ps resolution and µs-level dynamic range is under development. The sub-ps resolution is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method utilizing a pair of digital-to-time converters (DTC), between which the propagation delay difference is implemented by digitally controlling the unit load capacitors of their delay cells and also by digitally controlling the discharge current of the load capacitances. The research work focuses on improving the dynamic range and linearity of the DTC.

To increase the linear dynamic range of the DTC, the output inverter has been replaced with a comparator. Instead of using the process parameters dependent threshold voltage of an inverter to detect the discharging of the load capacitance C_L, a comparator with a stable reference voltage V_ref is used. According to the simulations, a linear dynamic range of 12-13 bits, i.e. several ns, with sub-ps resolution can be achieved with the comparator, because the comparator is much less sensitive to the slew rate of the input signal than the CMOS inverter. To further improve the resolution of the DTC, and to reduce the number of load capacitances, also the discharge current of the current starved inverter is digitally controlled. The overall operating point of the DTC is set by the bias current k×I_ref, where I_ref is a reference current, and k is the common control word set by a stabilizing loop to reach the desired dynamic range and resolution. The bias voltage of the previous design has been replaced by a current DAC (digital-to-analogue converter) to have digital control over the discharge current of the inverter. Furthermore, the discharge current can be scaled by a factor 2^q during conversion. This has the same effect as the scaling of capacitances, and this method is used after the minimum capacitance value has been reach in the conversion process. The load capacitance can be controlled either linearly, n×C_L, if we want to adjust the propagation delay of the DTC in general time interval generation, or as powers of two, 2ⁿ×C_L, as required by the binary search algorithm of successive approximation, see Figure 3.

 

Figure 3. Conceptual schematic diagram of the new DTC with sub-ps resolution and ns-level dynamic range.

 

A Time-to-Digital Converter Board Achieving 1 ps Measurement Precision

A time-to-digital converter based on time-to-amplitude interpolation was designed and tested. The converter was implemented with discrete components. The measurement range is about 0 - 328 μs with a state-of-the-art single shot precision of 1.5 ps. The time interval is measured by counting full clock cycles with a counter implemented in an FPGA circuit and the fractional time residue is then measured with time-to-amplitude converters that provide the picosecond level precision. The block diagram of the TDC is presented in Figure 4, and the actual realization in Figure 5.

Figure 4. Simplified block diagram of the TDC based on time-to-amplitude interpolation.

 

Figure 5. The TDC board (10 cm * 10 cm).

 

The interpolators consist of a constant current source, a fast switch, a Miller integrator and offset compensation circuitry. The interpolator charges a capacitor with a constant current during the fractional time residue. The output voltage of the interpolator is then AD converted and combined with the result of the full cycle counter. With a reference clock of 200 MHz, the measurement range of a single time-to-amplitude interpolator is 5 ns. All the bias voltages are produced by DA-converters that can be controlled via software. The nonlinearities of the interpolators reduce the single shot precision to about 1.5 picoseconds. The integral nonlinearities of the TACs are shown in Figure 6. When this systematic INL error is compensated, single-shot precision can be improved to ~1 ps.

 

Figure 6. INL of the time-to-amplitude converters.

 

Figure 7 shows the distribution of measurement results when a constant delay of 396 ns was measured. The standard deviation of the INL compensated results corresponds to a single-shot precision of 0.9 ps. This result is believed to represent the state-of-the-art among published time-to-digital converters.

 

Figure 7. Distribution of time interval measurement results.

 

An Integrated Laser Radar Chip

A CMOS laser radar chip, including an optical receiver channel and a time to digital converter (TDC) integrated onto the same die, and realized using a 0.13 µm CMOS technology has been tested as the part of a pulsed time-of-flight (TOF) laser rangefinder. The CMOS laser radar chip is based on a receiver channel using a slew rate measurement for the walk error compensation.

The linearity of the laser radar system was measured by sweeping a target from 1 meter to 21 meters with a 0.5 meter step and with a one meter step using a white paper and a diamond grade reflective sheet as targets, respectively. The dynamic range of more than 1:2000 could be achieved in this measurement. Figure 8a shows the accuracy of the measured results as a function of the distance with  the white paper (black line) and the diamond grade reflective sheet (grey line) used as targets. The accuracy of the system is better than +/- 5 mm from 4 m to 21 m. Peaks at the distance of approximately 2 m are due to disturbance from the comparator of the discrete start channel.

 The precision of the laser radar chip was measured over the whole dynamic range 1:10000 by using an optical density filter with two different threshold values of the comparator used for walk error compensation (the threshold value of a stop channel comparator multiplied by two and three). Figure 8b shows the measured single-shot precision standard deviation value as a  function of the signal amplitude of the received pulse with those two different threshold values 2*(SNR=10) and 3*(SNR=10). These curves include the jitter of the TDC, the jitter of the receiver channels (stop and walk error compensation channels) and the inaccuracy of the look-up table used for walk error compensation. The solid curve shows the single-shot precision standard deviation value of the stop channel, including of the jitter of the TDC and the receiver channel.

 

a)

b)

Figure 8. Linearity and precision of the laser radar receiver CMOS IC.

 

A Single Photon Avalanche Diode (SPAD) for Raman Spectroscopy

Several time gated single photon avalanche diode (SPAD) structures aimed for use in Raman spectroscopy were fabricated and tested in 0.35 µm HVCMOS technology. A SPAD can be implemented as a reverse biased p-n junction, and with a lightly doped guard ring can be used to prevent an unwanted surface breakdown. When the diode is biased above the breakdown voltage, even a single photon can induce the breakdown and can then be detected by conventional digital circuitry. In addition, a time-gate function was realized in the SPAD; this is because the output of the SPAD is read only during the short  laser pulse illumination to suppress the fluorescence background, typically dominating in the Raman spectra. This arrangement reduces also the dark count rate of the SPAD, resulting in a better SNR.

Figure 9 shows the layout of the SPAD die (a), and the cross section of a single SPAD (b). The diameters of the tested circular SPADs were 10 µm and 20 µm.  Figure 10 shows the dark count rates (DCR) of 10 µm and 20 µm (a) as a function of excess bias voltage (voltage above a breakdown). The dark count rates can be decreased by using time gating. The measured DCR of the 20 µm SPAD with a time gate window of 500 ps was measured to be 0.45 Hz, when a pulse rate of 120 kHz and an excess bias of 2.3 V were used. Experimental data of the reverse I-V characteristic is shown in Figure 10b, indicating a breakdown voltage of approximately 18.9 V. 

 

a)	b)
Figure 9. Layout and cross section of the CMOS SPAD.

 

a)

b)

Figure 10. Dark count rate and breakdown characteristics of the CMOS SPAD.

 

Generation of Electrical/Optical Transients

High-energy Picosecond Laser Diode Pulse Generation

In our recent work, we proposed a new laser diode structure that, based on its inherent properties, can produce with quite a simple driving scheme a ten-fold improvement in the achievable optical energy of a single picosecond optical pulse, compared to a standard laser diode configuration working in gain switching mode. The main idea is to utilize the structure with an extremely large active layer width (d_a) to optical confinement factor ratio (Г_a) (d_a/Г_a >> 1 μm).  Such a large value of the “equivalent spot size” (=d_a/Г_a) is rather unusual since it would in principle mean a higher steady state value for the lasing threshold current. The typical value of the equivalent spot size (d_a/Г_a) is ~1 mm for high power CW operated lasers, for example.

However, as we have shown, from the dynamic behavior point of view, the use of the specialized construction with d_a/Г_a >> 1 mm results in an increased time delay between threshold point and the beginning of the laser generation (“enhanced gain switching”). So we can accumulate more carriers in the active layer before beginning of the generation. As a result, higher pulse energy will be generated.

It is not however a trivial task to experimentally realize a structure with such a high value for d_a/Г_a. We have shown that in the cases of bulk or Quantum Well (QW) edge emitting lasers, this can be, in principle, achieved in strongly asymmetric waveguide structures which also have the advantage of supporting only a single fundamental transverse mode.

As an example of the performance that is available from this device, recent results obtained using a bulk GaAs/GaAlAs laser diode chip are shown in Figure 11. This test chip had no reflection coatings on its facets, and thus the total peak output power available in a single pulse was roughly twice that seen in Figure 11. As a result, a pulse with a peak power of >20 W (stripe width 120 mm) and width of less than 150 ps should be available in fundamental transverse mode from this bulk laser diode operating at about 850 nm with a pulse drive current of approx. 10 A.

 

Figure 11. Measured driving current and optical output pulses (only from the other edge) of the suggested DH bulk laser diode based on “enhanced gain-switching”.

 

A Unique GaAs Avalanche Switch: Efficiency, Stability and Reliability

A drastic reduction in the residual voltage (from ~100 V to a few volts) and a significant (factor of ~ two) increase in the dV/dt switching rate is demonstrated experimentally in the superfast (~200 ps) avalanche switching of a GaAs bipolar junction transistor (BJT) with an  increased emitter area, see Figure 12. This result is not a trivial one, as only a small number of conductive channels of a few microns in diameter participate in the transient independently of the emitter size, while the remaining (passive) part of the structure supplies the switching channels with the currents circulating inside the chip, which makes the impact ionization in the filaments more powerful.

 

Figure 12. Switching transient in specially designed and fabricated GaAs avalanche transistors with “small” and a “large” emitter areas [3].

 

Excellent agreement was found between the experiment and a specially developed quasi-3-D model, which provided a convincing physical explanation for drastic improvement in the switching efficiency, stability and reliability of a “large” area device with an increased emitter area, and also much lower power dissipation in the structure.

The transient thermal task in a GaAs avalanche BJT was achieved for the first time, and it was shown that only conic spreading of the “collapsing” field domain front (Figure 13) inside n⁺- substrate prevents overheating of the switching channels, while increase in the switching efficiency for the device of increased area limits the highest local temperature inside the structure to as a low value as ~400 K (Figure 14).

 

Figure 13. Penetration of the conic ionization front into an n+ subcollector reduces drastically the peak power dissipation.

 

Figure 14. Temperature profiles along the switching channels during the switching transient (a) in the transistor of “small” (b) and “large” (c) areas.

 

 

Another problem which is critically important for device reliability is an avalanche breakdown on the mesa-surface of the device, which may cause current instability leading to device destruction when the transistor is biased near the bulk breakdown voltage. We have found a new mechanism which suppresses the avalanche multiplication on a negatively beveled mesa surface (intrinsic of a GaAs avalanche BJT) and permits the bulk breakdown voltage to be achieved. This important phenomenon we termed Avalanche-assisted carrier trapping.

Avalanche-assisted Carrier Trapping on the Surface of a GaAs Avalanche BJT (ABJT)

This mechanism [11,12] consists in electron trapping on the deep surface acceptors, whose negative charge broadens the space-charge region on the surface, thus reducing the peak of the electric field and suppressing the breakdown process. Once started, the surface avalanche breakdown initiates negative feedback, which “softens” radically the breakdown I-V characteristics (Figure 15) and allows the voltage to be increased up to a volume breakdown value with a gradual increase in the surface current up to an acceptable level.

 

Figure 15. “Soft” surface breakdown of the collector-base junction of a GaAs avalanche BJT. Curves 1 and 1’ correspond to two samples: the highest and lowest currents observed in the experiment. Curves 2-4 simulated at different scenarios for initial charging of the surface traps along the mesa perimeter.

 

This mechanism allows using a GaAs avalanche BJT in the practically important case where technological conditions do not allow a guard ring or passivation layer to be formed on a negatively beveled mesa-surface.

3-D Phenomena in a Si ABJT

Currently Si ABJT’s are the commercial components most frequently used for nanosecond pumping of pulsed laser diodes. Surprisingly, we have only recently explained a comprehensive physical description of its operation at high currents using 1-D and 2-D approaches. Very lately, we have found additionally a trade-off between the switching efficiency of a Si ABJT in short-pulsing (~2 ns) mode, and its reliability with long (close to 10 ns), high-current (~100 A) pulses. This trade-off is determined in turn by a competition between two 3-D effects: one is the turn-on spread along emitter-base interface, and the other one is a competition between different parts of the perimeter with inhomogeneities according to “the winner takes all” principle. This work started a few years ago and now continues. We suggested earlier, and have lately shown [13] that turn-on spread, takes place indeed in the very beginning of the switching transient, while the second mechanism, which is more important for the reliability with long pulses, appears to be more complicated and its investigation requires further efforts. This activity is critically important for correct design of the transistor chips (and used circuitry) depending on the required switching parameters.     

THz Emission from a GaAs BJT Structure during its Avalanche Switching

Another very promising application for the avalanche switching mode in GaAs BJT is the generation of pulsed broad-band terahertz emission. Periodical nucleation and annihilation of ultra-narrow, powerfully ionizing “collapsing” domains is believed to cause the THz emission observed in our experiments. The task is very challenging and should be divided into several steps, most urgent and important of which is the correct characterization of the spectral power density in a broad spectral range. It requires development and characterization of a large number of band-pass spectral filters in the  sub-THz range, investigation of different transistor structures with different chip designs, etc.  A solution to those tasks is underway (see an example for one of the emitting transistors shown in Figure 16). In this particular case, a room-temperature quasi-optical detector based on a Schottky diode was used, while in general we use also specially designed high-speed NbN and MoRe  (low noise) bolometers and a Golay cell. The main applications of our future emitters we see in new generation 2-D and 3-D mm-wave and sub-mm wave imaging; the work in this direction has already started [14,15].

 

Figure 16. An example of a Schottky diode response on the emission of a GaAs ABJT passed through different narrow-band, band-pass filters. One can see that different spectral modes exhibit different waveforms.

 

Circuit Analysis Techniques and Results

Distortion Contribution Simulation Algorithm VoHB

Dr. Janne Aikio has been developing a general-purpose distortion contribution analysis called VoHB (Volterra on Harmonic Balance), and in 2009 it appeared as a functional, multi-device, model-independent prototype within AWR-Aplac’s analog simulator. During 2010, its capabilities have been extended, and it has been verified against many test circuits, whose distortion contributions have been previously hand-analyzed in the literature. Two journal publications are under preparation, and an example study of the ways found for improving the linearity of current-steering IF DA converters was reported in the Norchip 2010 conference.

The new capabilities of VoHB include support for a multi-tone and high-order analysis (e.g. a Doherty type RF power amplifier was simulated with 9th-order modeling), and adaptive building of polynomial models. In the latter, DC bias circuits are, for example, recognized and modeled with linear models, or VCCS elements (voltage-controlled current or charge sources) that have several, seriously correlating input signals are also recognized and characterized separately with somewhat perturbed test signals to break the correlation between the original control signals.

Furthermore, the polynomial models fitted by VoHB can be used for a traditional AC Volterra analysis, and this has been employed for a very fast harmonic load pull analysis. The implemented analysis can perform 5000 analyses (performed by Volterra analysis, but corresponding to a two-tone harmonic balance simulation) in two seconds. Such a high speed facilitates much more careful analysis of optimum harmonic matching, for example, and optimizing the linearity over a broad bandwidth range.

Design Methods for Switching Amplifiers

Lessons from a previously integrated GaAs RF PA were reported by Hietakangas in [10] in 2010. The research on switching amplifiers was continued. First, a rather exhaustive design space exploration was made for an inverse class E amplifier to see how sensitive switching amplifiers are to mistuning. It was found that with a broadband resistive load, the efficiency maximum is rather broad (and hence less sensitive to dimensioning errors), but if the load itself is seen through a narrowband  impedance matching network, the matching network seems to have a significant effect on the broadness of the optimum. This was a new finding, as the vast majority of publications just assume a broadband resistive load.

The research continued by studying the effects of non-linear output capacitance in a class E power amplifier, also in EER type applications. It was found that a non-linear output capacitance increases the peak voltage, and hence the voltage stress of the switch, and it also causes severe Vdd-PM distortion in EER type applications. It was also found that the very often suggested 50% duty cycle is not the only possibility, but both the level of the harmonics and the voltage stress can be reduced by extending the off-time of the switch.

By the end of the year, the study moved to the input side of a class E amplifier, and supply-modulated switching amplifiers were found to constitute a very difficult load: the fundamental tone input impedance varies very strongly with the supply voltage, and due to the resonant output network, the input impedance shows a negative real part. The output resonator also causes heavy 2^nd harmonic injection from drain to gate.

A researcher exchange carried out with Trondheim Technical University in 2009 has resulted in three joint publications.

Biomedical Applications

Olli Kursu began work in the Infotech Graduate School in 2010, and his area is – together with Dr. Mikko Vähäsöyrinki’s group at Dept. of Physics – the measurement of nerve signals of small animals. During 2010, he finalized and reported a servo positioning setup, where a small 3D piezo actuator setup is used to compensate for the movements of an insect to be monitored. Since that, he has been designing an integrated multi-channel nerve signal recorder for similar applications.

BIST (Built in Testing) of AD/DA Converters and Converter Pairs

In the doctoral thesis by Esa Korhonen, ways of testing converters without expensive precision instruments were studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) and integral non-linearity (INL) estimation was proposed. The algorithm assumes that two stimuli with constant offset between them are applied to the ADC under test, and that the code density histograms for both stimuli are recorded. The probability density function (PDF) of the stimulus is then solved using simple calculations so that the DNL and INL of the ADC can be estimated without a priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputs are digital, and the new algorithm can be used to characterize the INL and DNL of the DAC as well. This all-digital test configuration enables a simultaneous testing of both converters thanks to the new algorithm. One interesting application of the proposed test technique is the production testing of mixed-signal microcontrollers where the proposed calculation algorithm runs in the microcontroller and the only additional test hardware is the offset generator connected between the converters. The accuracy of the proposed method is limited by that of the offset between the stimuli. Therefore, an accurate and small offset generator was designed. The proposed on-chip offset generator is built using only four resistors and switches. It occupies 122x22 mm² in a 130 nm CMOS process, and accuracy is appropriate for the INL testing of 12-bit converters from rail-to-rail. In Fig. 17, the INL measurement results using the offset generator and 12-bit converters are shown.

 

Figure 17. Measured INL of a 12-bit DAC (upper) and ADC (lower) converter with the proposed method.

 

Linearization Studies and Experiments

Supply modulated RF transmitters

Timo Rautio summarized his results on supply-modulated RF transmitters in his Licentiate thesis in summer 2010. During the autumn, the group received a donation of a complete setup for driving envelope-tracking PAs, and this has been prepared for use in new, more broadband experiments. The group was also asked to beta-test a commercial PA characterization tool developed by a measuring instrument manufacturer, and this was conducted during autumn.

Digital Error Correction on A/D and D/A Converters

2010 was quite successful in the study of A/D and D/A converters. A previously started study on the use of partial histogram to linearize a segmented A/D converter was reported in the Master’s thesis by M. Kangas. M. Neitola wrote three journal papers, all accepted on different aspects of (a well-matured area of) multi-bit sigma-delta A/D and D/A converters.

First, a generalized data weighted algorithm (DWA) for shaping the mismatch noise (INL) in multi-bit ADCs was developed and reported in [9] – it is also published as a downloadable Simulink model. The algorithm applies equally well for low-pass and band-pass converters, and performs first-order mismatch noise shaping. Further, it was noticed that adding one additional unit element in the multi-bit thermometer-coded DAC (this was called incremental DWA or IDWA) cleans up spurious mismatch tones from the signal band, and this triggered additional studies and publications.

The literature study of different mismatch noise shaping algorithms showed that the reported results are not always repeatable, especially when a small set of random mismatch errors is used.   This led to the development of a more general and exhaustive test set for characterizing the performance of different DEM (dynamic element matching) algorithms. In short, a fixed set of different shaped INL responses is used (this avoids the need for long Monte-Carlo type analysis to gain statistical significance), and the performance is checked by a 2-D sweep over amplitude and signal frequency. The results are shown as “fingerprints” in Figure 18: here a) are low-pass and b) band-pass AD converters, and the oversampling ratios are 16, 32, and 64 from left to right. It is seen that the highest spurious tones (black area) move towards lower signal amplitudes when OSR is increased. The developed fingerprints provide a repeatable, exhaustive, and yet only moderately time-consuming method for comparing different DEM techniques. Also, a new, unit element utilization fingerprint was developed to test how sensitive the DEM algorithms are for repeating patterns.

 

Figure 18. Spurious tone fingerprints in a) low-pass and b) band-pass SD ADC. Black means high spurious tones due to mismatch noise.

 

The discovery of an IDWA structure triggered two studies on the origins of spurious tones  in SD converters in general. A theory that relates the signal amplitude and INL shape of a multi-bit DWA DAC to the frequency of the spurious tones has been accepted for publication, and will appear during 2011. A more general study relating the type of quantizer and the frequencies of the spurious tones is under development.

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Personnel

 

External Funding

 

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Doctoral Theses

Loikkanen M (2010) Design and compensation of high performance class AB amplifiers. Acta Universitatis Ouluensis C356.

Korhonen E (2010) On-chip testing of A/D and D/A converters. Acta Universitatis Ouluensis C365.

 

Selected Publications

Kozmin K, Johansson J & Kostamovaara J (2010) A low propagation delay dispersion comparator for a level-crossing AD converter.  Analog Integrated Circuits and Signal Processing 62(1): 51-61. ¹

Korhonen E, Carsten W & Kostamovaara J (2010) Combining the standard histogram method and a stimulus identification algorithm for A/D converter INL testing with a low-quality sine wave stimulus. IEEE Transactions on Circuits and Systems I 56(6): 1166-1174. ²

Vainshtein S, Yuferev V, Kostamovaara J, Kulagina M & Moilanen H (2010) Significant effect of emitter area on the efficiency, stability and realiability of picosecond switching in a GaAs bipolar transistor structure. IEEE Transactions on Electron Devices 57(4): 733-741. ³

Hallman LW, Ryvkin B, Haring K, Ranta S, Leinonen T & Kostamovaara J (2010) Asymmetric waveguide laser diode operated in gain switching mode demonstrates high power optical pulse generation. Electronics Letters 46(1): 65-66. ⁴

Nissinen I & Kostamovaara J (2010) Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter. Analog Integrated Circuits and Signal Processing 64(3): 271-280. ⁵

Korhonen E & Kostamovaara J (2010) On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs. Analog Integrated Circuits and Signal Processing (OnlineFirst). DOI: 10.1007/s10470-010-9496-2, 9 p. ⁶

Kostamovaara J (2010) Interview. Electronics Letters 46(1):4. ⁷

Neitola M, Rahkonen T & Raappana J (2010) A qualification approach to DAC mismatch shaping methods. IEEE Trans. on Circ. Syst.-II 57(11): 858-862. ⁸

Neitola M & Rahkonen T (2010) A generalized data weighted averaging algorithm. IEEE Trans. on Circ. Syst.-II 57(2): 115-119. ⁹

Hietakangas S, Typpö J & Rahkonen T (2010) Design of integrated 1.6 GHz, 2W tuned RF power amplifier. Analog Integrated Circuits and Signal Processing 64(3). ¹⁰

Duan G, Vainshtein S & Kostamovaara J (2011) Peculiarities of surface breakdown in GaAs bipolar junction structures. conditionally (mandatory changes) accepted for publication in IEEE Trans. Electr. Dev. MS#TED-2010-12-0876-R. ¹¹

Duan G, Vainshtein S & Kostamovaara J (2010) Physical interpretation of “soft” surface breakdown typical of GaAs avalanche transistors. Annual Journ. of Electronics (ISSN 1313-1842), Book 1, 22-25. ¹²

Duan G, Vainshtein S & Kostamovaara J (2010) Self-organizing of avalanche transistor operating area in accordance with parameters of external circuit. Annual Journ. of Electronics (ISSN 1313-1842), Book 1, 26-29. ¹³

Vainshtein S & Kostamovaara J & Yuferev V (2011) Nanosecond pulses for sub-terahertz imaging from avalanching GaAs bipolar transistors. Chapter 26 in Terahertz and Mid Infrared Radiation/Generation, Detection and Applications Series: NATO Science for Peace and Security Series B: Physics and Biophysics. ¹⁴Vainshtein S, Yuferev V, Kostamovaara J & Palankovski V (2010) Collapsing field domains in avalanche GaAs transistor: peculiar phenomenon and prospective applications. Annual Journ. of Electronics (ISSN 1313-1842), Book 1, 11-16. Plenary talk at 19th international conference ET 2010. ¹⁵